From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web10.8961.1678172101119966546 for ; Mon, 06 Mar 2023 22:55:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=EafQHK0N; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678172100; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5JSbApJKQ4zAtlNHHfP07oIs79qHR0ojVmsG8nTTqEE=; b=EafQHK0N8AwJjNSxXnNg6am6rl6ZXi0fvkbHY97RX2/X7u5CofKpn8ps/dZST+A9mBBxqJ 5PVhcs1D5vYWarfY+yBnny8LP4gPWUFsj/QJHTwtqvQjitYKrvcib+ZOI/Z9mJWp/wQuDP LTczLV/7OH/hIJpaMo+Z4yYcdg5RzZM= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-212-KreJ0fXSPu-NxcnnR6CeXQ-1; Tue, 07 Mar 2023 01:54:57 -0500 X-MC-Unique: KreJ0fXSPu-NxcnnR6CeXQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5D74D85A588; Tue, 7 Mar 2023 06:54:56 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1D7E340C10FA; Tue, 7 Mar 2023 06:54:56 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id E9091180092D; Tue, 7 Mar 2023 07:54:54 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Tom Lendacky , Jiewen Yao , Erdem Aktas , Anthony Perard , Gerd Hoffmann , Jordan Justen , Oliver Steffen , Min Xu , Michael Roth , James Bottomley , Pawel Polawski , Ard Biesheuvel , Julien Grall Subject: [PATCH v2 1/3] OvmfPkg/PlatformInitLib: update address space layout comment Date: Tue, 7 Mar 2023 07:54:52 +0100 Message-Id: <20230307065454.1434251-2-kraxel@redhat.com> In-Reply-To: <20230307065454.1434251-1-kraxel@redhat.com> References: <20230307065454.1434251-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true Move the commment up so it is placed just before the address space calculations start. Also add q35 memory layout. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/Platform.c | 36 ++++++++++++---------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c index 9fee6e481038..678e8e329023 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -152,26 +152,12 @@ PlatformMemMapInitialization ( return; } - PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); - PciExBarBase = 0; - if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { - // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. - // - PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); - ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase); - ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); - PciBase = (UINT32)(PciExBarBase + SIZE_256MB); - } else { - ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base); - PciBase = PlatformInfoHob->Uc32Base; - } - // // address purpose size // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) (pc) + // 0xB0000000 MMCONFIG 256 MB (q35) + // 0xC0000000 PCI MMIO 960 MB (q35) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB @@ -181,6 +167,22 @@ PlatformMemMapInitialization ( // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PciExBarBase = 0; + if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + // + // The MMCONFIG area is expected to fall between the top of low RAM and + // the base of the 32-bit PCI host aperture. + // + PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); + ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase); + ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); + PciBase = (UINT32)(PciExBarBase + SIZE_256MB); + } else { + ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base); + PciBase = PlatformInfoHob->Uc32Base; + } + PciSize = 0xFC000000 - PciBase; PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); -- 2.39.2