From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web11.8924.1678172104897140610 for ; Mon, 06 Mar 2023 22:55:05 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=E9k9r3pB; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678172103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yDb4FWtW37Y3tIktPrYLu4l0698G5kvt2VwcX0203fI=; b=E9k9r3pBHvhyFeTg0neaQMEOrYngYSzbW2nXRR3TOBEXEyQSGZIEm87zBCdsb8ahmR5bFZ AJ82OW5nxeVX0+R+ojpkSZAtdmxNti5/LxHCYd7N11pDM4gTRKnyODDPqincKbLVYzv5Wi ApecvLzgie9lW2RbLSriod3ER2sfuV0= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-230-LQ5_jmnpMQi_2laYFlp7iQ-1; Tue, 07 Mar 2023 01:54:58 -0500 X-MC-Unique: LQ5_jmnpMQi_2laYFlp7iQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 01A8E3806635; Tue, 7 Mar 2023 06:54:58 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8D9D0C15BAE; Tue, 7 Mar 2023 06:54:57 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id EE9F11800931; Tue, 7 Mar 2023 07:54:54 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Tom Lendacky , Jiewen Yao , Erdem Aktas , Anthony Perard , Gerd Hoffmann , Jordan Justen , Oliver Steffen , Min Xu , Michael Roth , James Bottomley , Pawel Polawski , Ard Biesheuvel , Julien Grall Subject: [PATCH v2 2/3] OvmfPkg/PlatformInitLib: move mmconfig to 0xe0000000 Date: Tue, 7 Mar 2023 07:54:53 +0100 Message-Id: <20230307065454.1434251-3-kraxel@redhat.com> In-Reply-To: <20230307065454.1434251-1-kraxel@redhat.com> References: <20230307065454.1434251-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true Also swap the ordering of 32bit PCI MMIO window on q35, i.e. use the room between end of low memory and the start of the mmconfig bar. With a typical configuration on modern qemu with gigabyte-aligned memory the MMIO window start at 0x8000000, sized 1532 MB. In case there is memory present above 0x80000000 the window will start at 0xc0000000 instead, with 512 MB size. This depends on qemu commit 4a4418369d6d ("q35: fix mmconfig and PCI0._CRS"), so it raises the bar for the lowest supported version to qemu 4.1 (released Aug 2019). Signed-off-by: Gerd Hoffmann --- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 2 +- OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 2 +- OvmfPkg/OvmfXen.dsc | 2 +- OvmfPkg/Library/PlatformInitLib/Platform.c | 10 +++++----- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 1cebd6b4bcc2..e8481ba8cdf3 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -443,7 +443,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if $(SOURCE_DEBUG_ENABLE) == TRUE gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX64.dsc index 95b9594ddce0..6fea54bb0b6b 100644 --- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc +++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc @@ -448,7 +448,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 # # The NumberOfPages values below are ad-hoc. They are updated sporadically at diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 22dc29330d2d..fff3e13151ad 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -560,7 +560,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if $(SOURCE_DEBUG_ENABLE) == TRUE gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 6b539814bdb0..169b9b9c2beb 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -565,7 +565,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if $(SOURCE_DEBUG_ENABLE) == TRUE gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index e3c64456dfef..12b88b71ab7f 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -586,7 +586,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if $(SOURCE_DEBUG_ENABLE) == TRUE gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index c328987e8432..18144d9a6d94 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -434,7 +434,7 @@ [PcdsFixedAtBuild] # # On Q35 machine types that QEMU intends to support in the long term, QEMU # never lets the RAM below 4 GB exceed 2816 MB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if $(SOURCE_DEBUG_ENABLE) == TRUE gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c index 678e8e329023..5cf8af825a2f 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -156,8 +156,8 @@ PlatformMemMapInitialization ( // address purpose size // ------------ -------- ------------------------- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) (pc) - // 0xB0000000 MMCONFIG 256 MB (q35) - // 0xC0000000 PCI MMIO 960 MB (q35) + // max(top, 2g) PCI MMIO 0xE0000000 - max(top, 2g) (q35) + // 0xE0000000 MMCONFIG 256 MB (q35) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB @@ -168,6 +168,7 @@ PlatformMemMapInitialization ( // 0xFEE00000 LAPIC 1 MB // PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PciBase = PlatformInfoHob->Uc32Base; PciExBarBase = 0; if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // @@ -177,13 +178,12 @@ PlatformMemMapInitialization ( PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress); ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); - PciBase = (UINT32)(PciExBarBase + SIZE_256MB); + PciSize = (UINT32)(PciExBarBase - PciBase); } else { ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base); - PciBase = PlatformInfoHob->Uc32Base; + PciSize = 0xFC000000 - PciBase; } - PciSize = 0xFC000000 - PciBase; PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); PlatformInfoHob->PcdPciMmio32Base = PciBase; -- 2.39.2