From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web11.8922.1678172100877670745 for ; Mon, 06 Mar 2023 22:55:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=LLldG6/U; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678172099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HXtBjxcVIAqRSR7tUYyUl6XNYlhoxz581KvxW2dDcXw=; b=LLldG6/UPF8P7ugp3HJTpSIaqdM/6NSjroHwpyR/CfKk0Wo8AHGJz0SQoeKtLITCTuNiTO momayRQI4Mh80xDs4avAs5IwcgbDnxxcDBY1RfFPlzybeQL0K5gjF1mI/GRI93n/89/SaN 1Xw2Ta/KKBNKxFzklwCwWjTd8cZJhfo= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-460-k7CMJASMPxanSHnVbYV2dQ-1; Tue, 07 Mar 2023 01:54:58 -0500 X-MC-Unique: k7CMJASMPxanSHnVbYV2dQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C75CC280AA2A; Tue, 7 Mar 2023 06:54:57 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8ECDD14171C3; Tue, 7 Mar 2023 06:54:57 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id F262E180093B; Tue, 7 Mar 2023 07:54:54 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Tom Lendacky , Jiewen Yao , Erdem Aktas , Anthony Perard , Gerd Hoffmann , Jordan Justen , Oliver Steffen , Min Xu , Michael Roth , James Bottomley , Pawel Polawski , Ard Biesheuvel , Julien Grall Subject: [PATCH v2 3/3] OvmfPkg/PlatformInitLib: simplify mtrr setup Date: Tue, 7 Mar 2023 07:54:54 +0100 Message-Id: <20230307065454.1434251-4-kraxel@redhat.com> In-Reply-To: <20230307065454.1434251-1-kraxel@redhat.com> References: <20230307065454.1434251-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true With the new mmconfig location at 0xe0000000 above the 32-bit PCI MMIO window we don't have to special-case the mmconfig xbar any more. We'll just add a mtrr uncachable entry starting at MMIO window base and ending at 4GB. Update comments to match reality. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 36 +++++++++------------ 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index 38cece9173e8..f85a63ac5130 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -61,33 +61,20 @@ PlatformQemuUc32BaseInitialization ( return; } + ASSERT ( + PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID || + PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID + ); + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= PlatformInfoHob->LowMemory); - - if (PlatformInfoHob->LowMemory <= BASE_2GB) { - // Newer qemu with gigabyte aligned memory, - // 32-bit pci mmio window is 2G -> 4G then. - PlatformInfoHob->Uc32Base = BASE_2GB; - } else { - // - // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of - // variable MTRRs (preferably 1 or 2). - // - PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress); - } - - return; } - ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID); // - // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one + // Start with the [LowerMemorySize, 4GB) range. Make sure one // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // @@ -1027,6 +1014,13 @@ PlatformQemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs to // cover it exactly. // + // Because of that PlatformQemuUc32BaseInitialization() will round + // up PlatformInfoHob->LowMemory to make sure a single mtrr register + // is enough. The the result will be stored in + // PlatformInfoHob->Uc32Base. On a typical qemu configuration with + // gigabyte-alignment being used LowMemory will be 2 or 3 GB and no + // rounding is needed, so LowMemory and Uc32Base will be identical. + // if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID)) { MtrrGetAllMtrrs (&MtrrSettings); @@ -1056,8 +1050,8 @@ PlatformQemuInitializeRam ( ASSERT_EFI_ERROR (Status); // - // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI - // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. + // Set the memory range from the start of the 32-bit PCI MMIO + // aperture to 4GB as uncacheable. // Status = MtrrSetMemoryAttribute ( PlatformInfoHob->Uc32Base, -- 2.39.2