From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3482.1678270163429735420 for ; Wed, 08 Mar 2023 02:09:25 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=C5OfIkG0; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678270165; x=1709806165; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6v13B73n920a8vTZVkyqTvVepkjkC+PpcEPeHR8flsg=; b=C5OfIkG0ej1TEil6jK8l/aMHmW8mMEmoqLqnmnUHRH4l4fV5rWq4AOli 8RZgK55Kze6tuOzx/uURFHyqP0DUMFTRuSlq4DMsHLL/6/+sgJzK4xwAF WfqxuhSbLoNdNZtyE+PhbHcLKfDVp03uqEZ2ZQrCK3SNLxH+ErbPm2m7y Rgiu/3gItnpNGxuOeKxoerk6y/BKm+dbzCbJSLZZvH98tzAIA5P9ZOJTU ij/pFrEeGo5c7IuAvoIOb4XP4mN7CMucUKmKd2telYi2yx4t9r/lMvO7Y /w/htZDob2cPUB2yaF4LvHymk8OcoG2usrWU2vmRMuupZ10m9684wiMbA A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442846" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442846" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862858" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862858" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:09:20 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V2 11/14] UefiCpuPkg/CpuPageTableLib: Enable PAE paging Date: Wed, 8 Mar 2023 18:07:55 +0800 Message-Id: <20230308100758.669-12-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Remove the limitation check for PagingPae to enable creating or updating PAE page table in CpuPageTableLib. The origin code is naturally adapted for PAE paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 4e8ac9b981..d99a21a0fc 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -658,10 +658,9 @@ PageTableMap ( return RETURN_SUCCESS; } - if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode >= PagingModeMax)) { + if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return RETURN_UNSUPPORTED; } @@ -694,11 +693,11 @@ PageTableMap ( MaxLeafLevel = (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel = (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); - MaxLinearAddress = LShiftU64 (1, 12 + MaxLevel * 9); + MaxLinearAddress = (PagingMode == PagingPae) ? LShiftU64 (1, 32) : LShiftU64 (1, 12 + MaxLevel * 9); if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - LinearAddress)) { // - // Maximum linear address is (1 << 48) or (1 << 57) + // Maximum linear address is (1 << 32), (1 << 48) or (1 << 57) // return RETURN_INVALID_PARAMETER; } @@ -771,6 +770,14 @@ PageTableMap ( IsModified ); if (!RETURN_ERROR (Status)) { + if (PagingMode == PagingPae) { + // + // These fields of PAE paging PDPTE should be 0 according to SDM. + // + TopPagingEntry.PdptePae.Bits.MustBeZero = 0; + TopPagingEntry.PdptePae.Bits.MustBeZero2 = 0; + } + *PageTable = (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MASK_40); } -- 2.31.1.windows.1