From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.3470.1678270139326397803 for ; Wed, 08 Mar 2023 02:08:59 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=m6IueO5z; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678270139; x=1709806139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a7PJqMHwoM/V/aEmnWHH05M/wBr3cm2G8Lq68+7PxvM=; b=m6IueO5zrwB8lB0+CMRwyw+zWzcJ2rsDUSyyhGfdSdp6y0ZcjTqkq+Wn 1U3ZYFFzyaTJszyF8ZCfvnYPmDhtKSlEwYz8u+mdbce40DYrqLGb4WVaC uFBQAVWKD6Dsr1Je+4yCqpeH64Swv+b0CsicZFCmTv6ar3dOM7tkbVslD m8YvLd8ZMAE+ZVFLo5eiOG0grEIMGBMs9oj9nlB3adINb+GRlo3bVN/Cf zOmZ7C8UUiqXxCeXTZGtArQSIERETCt0qAL9yJxvnZsIIVuxca9nqFTiR dhy7g0yoH5U3F6r+3yLNJBbfwUHtFb6+Nlhe9WMqdk1wlq2EO9UhdZT34 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="338442648" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="338442648" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="745862628" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="745862628" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 02:08:56 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V2 03/14] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Wed, 8 Mar 2023 18:07:47 +0800 Message-Id: <20230308100758.669-4-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230308100758.669-1-dun.tan@intel.com> References: <20230308100758.669-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 4c9d70fa0a..ee27238edb 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 = ParentAttribute->Uint64; ParentAttribute = &LocalParentAttribute; + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12). + // + BitStart = 12 + (Level - 1) * 9; + PagingEntryIndex = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1); + RegionLength = REGION_LENGTH (Level); + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits // when Modify is FALSE. @@ -325,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory type. // PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) - == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) + == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress == 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength) + == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)))) { // // This function is called when the memory length is less than the region length of the parent level. @@ -353,8 +364,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask); - RegionLength = REGION_LENGTH (Level); - PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset = 0, Index = 0; Index < 512; Index++) { PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; SubOffset += RegionLength; @@ -425,14 +435,11 @@ PageTableLibMapInLevel ( } // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLength and lower than (LinearAddress + Offset). // - BitStart = 12 + (Level - 1) * 9; - Index = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1); - RegionLength = LShiftU64 (1, BitStart); - RegionMask = RegionLength - 1; - RegionStart = (LinearAddress + Offset) & ~RegionMask; + Index = PagingEntryIndex; + RegionMask = RegionLength - 1; + RegionStart = (LinearAddress + Offset) & ~RegionMask; ParentAttribute->Uint64 = PageTableLibGetPnleMapAttribute (&ParentPagingEntry->Pnle, ParentAttribute); -- 2.31.1.windows.1