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From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: devel@edk2.groups.io
Cc: Andrei Warkentin <andrei.warkentin@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH v5 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec
Date: Fri, 10 Mar 2023 11:04:56 -0600	[thread overview]
Message-ID: <20230310170456.5230-4-andrei.warkentin@intel.com> (raw)
In-Reply-To: <20230310170456.5230-1-andrei.warkentin@intel.com>

If the SerialPortLib had any initialization needed, this
would be skipped in the RiscVVirt Sec. Follow the example
seen elsewhere (ArmVirtPkg PrePi).

Seen with BaseSerialPortLibRiscVSbi not using DBCN in Sec, yet
using DBCN elsewhere.

Cc: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
 OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
 OvmfPkg/RiscVVirt/Sec/SecMain.h   | 1 +
 OvmfPkg/RiscVVirt/Sec/SecMain.c   | 4 +++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3af596..0e2a5785e8a4 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -48,6 +48,7 @@ [LibraryClasses]
   FdtLib
   MemoryAllocationLib
   HobLib
+  SerialPortLib
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid                # PPI ALWAYS_PRODUCED
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h
index 83a8058efe40..7c7650f0d298 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.h
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h
@@ -29,6 +29,7 @@
 #include <Library/PrePiLib.h>
 #include <Library/PlatformInitLib.h>
 #include <Library/PrePiHobListPointerLib.h>
+#include <Library/SerialPortLib.h>
 #include <Register/RiscV64/RiscVImpl.h>
 
 /**
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c
index adf73f2eb66c..b35c77774510 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.c
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   RISC-V SEC phase module for Qemu Virt.
 
-  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -57,6 +57,8 @@ SecStartup (
   UINT64                      StackBase;
   UINT32                      StackSize;
 
+  SerialPortInitialize ();
+
   //
   // Report Status Code to indicate entering SEC core
   //
-- 
2.25.1


      parent reply	other threads:[~2023-03-10 17:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-10 17:04 [PATCH v5 0/3] RISC-V SBI-backed SerialLib Andrei Warkentin
2023-03-10 17:04 ` [PATCH v5 1/3] MdePkg: BaseRiscVSbiLib: make more useful to consumers Andrei Warkentin
2023-03-10 17:04 ` [PATCH v5 2/3] MdePkg: add SBI-based SerialPortLib for RISC-V Andrei Warkentin
2023-03-17  4:53   ` Andrei Warkentin
2023-03-17  5:00     ` Michael D Kinney
2023-03-17  5:44       ` Andrei Warkentin
2023-03-27 16:32         ` Michael D Kinney
2023-03-28 20:00           ` Andrei Warkentin
2023-03-28 20:09             ` Michael D Kinney
2023-03-28 20:20               ` Andrei Warkentin
2023-03-28 21:25                 ` Michael D Kinney
2023-03-28 22:00                   ` Andrei Warkentin
     [not found]       ` <174D1E9AD1BD3A96.10271@groups.io>
2023-03-27 16:10         ` [edk2-devel] " Andrei Warkentin
2023-03-10 17:04 ` Andrei Warkentin [this message]

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