From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.24949.1678467923451353633 for ; Fri, 10 Mar 2023 09:05:24 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=KRSzN3ew; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678467924; x=1710003924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h/4nVVTnFbZEkMdsYyXXSIlPFC3bykkooTPagd6gayQ=; b=KRSzN3ewOM6gwSCJEsyySyZRZasYJbNQoyrfIUPcHt1niqkMUVobDHd7 Qpv8CU4jJhdFHTj/iOFA0Rj+ncW4HucOn5NlCZUiIiJAYg4QHcdkRL6QE Tw61IBXylfwyPligm1hXxl3iczxsXxZz2yvSE0Kn5C5aVX6zc0+4vbgqX g4cbCRnDyIMikH0NaGVXg2sPZI4iZH+CDCYFgX77oElz8hm/nLIzzGpak zpxNGtQInyivnrw0d7ukqGg/W2yagNl13HbZrHAdqU9NaLDJx1W7d+adD /IdsaS/5v+njAT6R3RZ0OawpytOB0/wFAUul4tUxZpBflqk+rGjsvdHVT A==; X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="364432131" X-IronPort-AV: E=Sophos;i="5.98,250,1673942400"; d="scan'208";a="364432131" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2023 09:05:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="821132854" X-IronPort-AV: E=Sophos;i="5.98,250,1673942400"; d="scan'208";a="821132854" Received: from awarkent-mobl1.amr.corp.intel.com ([10.212.10.237]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2023 09:05:12 -0800 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Sunil V L Subject: [PATCH v5 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Date: Fri, 10 Mar 2023 11:04:56 -0600 Message-Id: <20230310170456.5230-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310170456.5230-1-andrei.warkentin@intel.com> References: <20230310170456.5230-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbi not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Reviewed-by: Sunil V L Signed-off-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af596..0e2a5785e8a4 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ [LibraryClasses] FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe40..7c7650f0d298 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index adf73f2eb66c..b35c77774510 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // -- 2.25.1