From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
zhiguang.liu@intel.com, sunilvl@ventanamicro.com,
git@danielschaefer.me, andrei.warkentin@intel.com,
Tuan Phan <tphan@ventanamicro.com>
Subject: [PATCH v2] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated
Date: Fri, 10 Mar 2023 13:50:19 -0800 [thread overview]
Message-ID: <20230310215019.29783-1-tphan@ventanamicro.com> (raw)
In-Reply-To: <ZArHTn/3aNyuPdzk@sunil-laptop>
When the range instruction cache invalidating not supported, the whole
instruction cache should be invalidated instead.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
V2:
- Format with uncrustify.
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 67a3387ff3c6..09de53fb5687 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -76,7 +76,12 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ DEBUG (
+ (DEBUG_WARN,
+ "%a:RISC-V unsupported function.\n"
+ "Invalidating the whole instruction cache instead.\n", __func__)
+ );
+ InvalidateInstructionCache ();
return Address;
}
--
2.25.1
next prev parent reply other threads:[~2023-03-10 21:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-06 17:10 [PATCH] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated Tuan Phan
2023-03-10 5:59 ` Sunil V L
2023-03-10 21:50 ` Tuan Phan [this message]
2023-03-15 5:21 ` [PATCH v2] " Sunil V L
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