From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.41536.1678524863347576133 for ; Sat, 11 Mar 2023 00:54:23 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=IB62RoA4; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678524863; x=1710060863; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tYtsFrKJR/3Y9csG8TOHPvttC15J0xe1XUQRZRAlcKY=; b=IB62RoA4YQk0D0NuRnKWFDkGRLTZcG4TAxfncFbhRmVdvtPSyb5E3YGD sWy7sIFpA/zU0pfscAmO345UGcC6mLr3VBkoBDJTS8o8JmyRKaPS1eMUW iZ2846gpV/aqDYsh934d6GM1NFvz1r0vj0P4VNlyXzz+7WThEmh7RBtBi 7f82J1yPYxnsjQhMm5K5a7JPcGX4nQnHl4pGD4dWta4MK2sAybac+Ctvq SEen3+uOp4UT0gjdKP+Cu5ojkfUapDBDJhu/57gSFMOaVvBGBl9eY+wk4 wVTIPLiSdkeyTRdnxXtsNyyB7MGVsxqOs+OhU/8c2c8CZo2IjM1aiFow3 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="316533375" X-IronPort-AV: E=Sophos;i="5.98,252,1673942400"; d="scan'208";a="316533375" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2023 00:54:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="708301873" X-IronPort-AV: E=Sophos;i="5.98,252,1673942400"; d="scan'208";a="708301873" Received: from evanccy.ccr.corp.intel.com ([10.238.200.73]) by orsmga008.jf.intel.com with ESMTP; 11 Mar 2023 00:54:19 -0800 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Andrei Warkentin , Sunil V L Subject: [PATCH 2/3] Platform/SiFive: align the library and driver to MdePkg Date: Sat, 11 Mar 2023 16:53:48 +0800 Message-Id: <20230311085349.607-2-evan.chai@intel.com> X-Mailer: git-send-email 2.39.0.windows.2 In-Reply-To: <20230311085349.607-1-evan.chai@intel.com> References: <20230311085349.607-1-evan.chai@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable There are almost same implementation in MdePkg, the part in platform package can be deprecated. Cc: Daniel Schaefer Signed-off-by: Evan Chai Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- .../RiscVTimerLib/BaseRiscVTimerLib.inf | 35 -- .../Library/RiscVTimerLib/RiscVTimerLib.c | 201 ------------ .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 13 +- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 310 ------------------ .../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 198 ----------- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 49 --- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.uni | 13 - .../Universal/CpuDxe/CpuDxeExtra.uni | 14 - 8 files changed, 6 insertions(+), 827 deletions(-) delete mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseR= iscVTimerLib.inf delete mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscV= TimerLib.c delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtr= a.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTim= erLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf deleted file mode 100644 index 3c61149d..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.i= nf +++ /dev/null @@ -1,35 +0,0 @@ -## @file=0D -# RISC-V Timer Library Instance.=0D -#=0D -# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x0001001b=0D - BASE_NAME =3D BaseRiscVTimerLib=0D - FILE_GUID =3D F0450728-3221-488E-8C63-BD3A8DF500E2=0D - MODULE_TYPE =3D BASE=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D TimerLib=0D -=0D -[Sources]=0D - RiscVTimerLib.c=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D -=0D -[Pcd]=0D - gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond=0D - gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - PcdLib=0D - RiscVCpuLib=0D - MachineModeTimerLib=0D -=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c deleted file mode 100644 index 40a04d60..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c +++ /dev/null @@ -1,201 +0,0 @@ -/** @file=0D - RISC-V instance of Timer Library.=0D -=0D - Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D - Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Stalls the CPU for at least the given number of ticks.=0D -=0D - Stalls the CPU for at least the given number of ticks. It's invoked by=0D - MicroSecondDelay() and NanoSecondDelay().=0D -=0D - @param Delay A period of time to delay in ticks.=0D -=0D -**/=0D -VOID=0D -InternalRiscVTimerDelay (=0D - IN UINT32 Delay=0D - )=0D -{=0D - UINT32 Ticks;=0D - UINT32 Times;=0D -=0D - Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2);=0D - Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);=0D - do {=0D - //=0D - // The target timer count is calculated here=0D - //=0D - Ticks =3D RiscVReadMachineTimerInterface () + Delay;=0D - Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2);=0D - while (((Ticks - RiscVReadMachineTimerInterface ()) & (1 << (RISCV_TIM= ER_COMPARE_BITS - 1))) =3D=3D 0) {=0D - CpuPause ();=0D - }=0D - } while (Times-- > 0);=0D -}=0D -=0D -/**=0D - Stalls the CPU for at least the given number of microseconds.=0D -=0D - Stalls the CPU for the number of microseconds specified by MicroSeconds.= =0D -=0D - @param MicroSeconds The minimum number of microseconds to delay.=0D -=0D - @return MicroSeconds=0D -=0D -**/=0D -UINTN=0D -EFIAPI=0D -MicroSecondDelay (=0D - IN UINTN MicroSeconds=0D - )=0D -{=0D - InternalRiscVTimerDelay (=0D - (UINT32)DivU64x32 (=0D - MultU64x32 (=0D - MicroSeconds,=0D - PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D - ),=0D - 1000000u=0D - )=0D - );=0D - return MicroSeconds;=0D -}=0D -=0D -/**=0D - Stalls the CPU for at least the given number of nanoseconds.=0D -=0D - Stalls the CPU for the number of nanoseconds specified by NanoSeconds.=0D -=0D - @param NanoSeconds The minimum number of nanoseconds to delay.=0D -=0D - @return NanoSeconds=0D -=0D -**/=0D -UINTN=0D -EFIAPI=0D -NanoSecondDelay (=0D - IN UINTN NanoSeconds=0D - )=0D -{=0D - InternalRiscVTimerDelay (=0D - (UINT32)DivU64x32 (=0D - MultU64x32 (=0D - NanoSeconds,=0D - PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D - ),=0D - 1000000000u=0D - )=0D - );=0D - return NanoSeconds;=0D -}=0D -=0D -/**=0D - Retrieves the current value of a 64-bit free running performance counter= .=0D -=0D - Retrieves the current value of a 64-bit free running performance counter= . The=0D - counter can either count up by 1 or count down by 1. If the physical=0D - performance counter counts by a larger increment, then the counter value= s=0D - must be translated. The properties of the counter can be retrieved from= =0D - GetPerformanceCounterProperties().=0D -=0D - @return The current value of the free running performance counter.=0D -=0D -**/=0D -UINT64=0D -EFIAPI=0D -GetPerformanceCounter (=0D - VOID=0D - )=0D -{=0D - return (UINT64)RiscVReadMachineTimerInterface ();=0D -}=0D -=0D -/**return=0D - Retrieves the 64-bit frequency in Hz and the range of performance counte= r=0D - values.=0D -=0D - If StartValue is not NULL, then the value that the performance counter s= tarts=0D - with immediately after is it rolls over is returned in StartValue. If=0D - EndValue is not NULL, then the value that the performance counter end wi= th=0D - immediately before it rolls over is returned in EndValue. The 64-bit=0D - frequency of the performance counter in Hz is always returned. If StartV= alue=0D - is less than EndValue, then the performance counter counts up. If StartV= alue=0D - is greater than EndValue, then the performance counter counts down. For= =0D - example, a 64-bit free running counter that counts up would have a Start= Value=0D - of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counte= r=0D - that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0.=0D -=0D - @param StartValue The value the performance counter starts with when i= t=0D - rolls over.=0D - @param EndValue The value that the performance counter ends with bef= ore=0D - it rolls over.=0D -=0D - @return The frequency in Hz.=0D -=0D -**/=0D -UINT64=0D -EFIAPI=0D -GetPerformanceCounterProperties (=0D - OUT UINT64 *StartValue, OPTIONAL=0D - OUT UINT64 *EndValue OPTIONAL=0D - )=0D -{=0D - if (StartValue !=3D NULL) {=0D - *StartValue =3D 0;=0D - }=0D -=0D - if (EndValue !=3D NULL) {=0D - *EndValue =3D 32 - 1;=0D - }=0D -=0D - return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);=0D -}=0D -=0D -/**=0D - Converts elapsed ticks of performance counter to time in nanoseconds.=0D -=0D - This function converts the elapsed ticks of running performance counter = to=0D - time value in unit of nanoseconds.=0D -=0D - @param Ticks The number of elapsed ticks of running performance cou= nter.=0D -=0D - @return The elapsed time in nanoseconds.=0D -=0D -**/=0D -UINT64=0D -EFIAPI=0D -GetTimeInNanoSecond (=0D - IN UINT64 Ticks=0D - )=0D -{=0D - UINT64 NanoSeconds;=0D - UINT32 Remainder;=0D -=0D - //=0D - // Ticks=0D - // Time =3D --------- x 1,000,000,000=0D - // Frequency=0D - //=0D - NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRisc= VMachineTimerFrequencyInHerz), &Remainder), 1000000000u);=0D -=0D - //=0D - // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000)=0D - // will not overflow 64-bit.=0D - //=0D - NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));=0D -=0D - return NanoSeconds;=0D -}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 0591cd6a..b8363c56 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -2,6 +2,7 @@ # RISC-V processor package.=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -39,11 +40,11 @@ !include MdePkg/MdeLibs.dsc.inc=0D =0D [LibraryClasses.common]=0D - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf=0D RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf=0D MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf=0D #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D @@ -81,20 +82,19 @@ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D =0D [LibraryClasses.common.DXE_CORE]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf=0D =0D [LibraryClasses.common.DXE_DRIVER]=0D PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf=0D =0D [LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf=0D =0D [LibraryClasses.common.UEFI_DRIVER]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf=0D =0D [Components]=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf= =0D Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandle= rDxeLib.inf=0D Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirm= wareContextSbiLib.inf=0D Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/Pe= iServicesTablePointerLibOpenSbi.inf=0D @@ -103,7 +103,6 @@ Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf=0D Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf= =0D =0D - Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf=0D Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf=0D Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf=0D Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c deleted file mode 100644 index 8d4d406e..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c +++ /dev/null @@ -1,310 +0,0 @@ -/** @file=0D - RISC-V CPU DXE driver.=0D -=0D - Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include "CpuDxe.h"=0D -=0D -//=0D -// Global Variables=0D -//=0D -STATIC BOOLEAN mInterruptState =3D FALSE;=0D -STATIC EFI_HANDLE mCpuHandle =3D NULL;=0D -=0D -EFI_CPU_ARCH_PROTOCOL gCpu =3D {=0D - CpuFlushCpuDataCache,=0D - CpuEnableInterrupt,=0D - CpuDisableInterrupt,=0D - CpuGetInterruptState,=0D - CpuInit,=0D - CpuRegisterInterruptHandler,=0D - CpuGetTimerValue,=0D - CpuSetMemoryAttributes,=0D - 1, // NumberOfTimers=0D - 4 // DmaBufferAlignment=0D -};=0D -=0D -//=0D -// CPU Arch Protocol Functions=0D -//=0D -=0D -/**=0D - Flush CPU data cache. If the instruction cache is fully coherent=0D - with all DMA operations then function can just return EFI_SUCCESS.=0D -=0D - @param This Protocol instance structure=0D - @param Start Physical address to start flushing from.=0D - @param Length Number of bytes to flush. Round up to chipset= =0D - granularity.=0D - @param FlushType Specifies the type of flush operation to perfo= rm.=0D -=0D - @retval EFI_SUCCESS If cache was flushed=0D - @retval EFI_UNSUPPORTED If flush type is not supported.=0D - @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuFlushCpuDataCache (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS Start,=0D - IN UINT64 Length,=0D - IN EFI_CPU_FLUSH_TYPE FlushType=0D - )=0D -{=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Enables CPU interrupts.=0D -=0D - @param This Protocol instance structure=0D -=0D - @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D - @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuEnableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D - )=0D -{=0D - EnableInterrupts ();=0D - mInterruptState =3D TRUE;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Disables CPU interrupts.=0D -=0D - @param This Protocol instance structure=0D -=0D - @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D - @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuDisableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D - )=0D -{=0D - DisableInterrupts ();=0D - mInterruptState =3D FALSE;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Return the state of interrupts.=0D -=0D - @param This Protocol instance structure=0D - @param State Pointer to the CPU's current interrupt st= ate=0D -=0D - @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D - @retval EFI_INVALID_PARAMETER State is NULL.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuGetInterruptState (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - OUT BOOLEAN *State=0D - )=0D -{=0D - if (State =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - *State =3D mInterruptState;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Generates an INIT to the CPU.=0D -=0D - @param This Protocol instance structure=0D - @param InitType Type of CPU INIT to perform=0D -=0D - @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D - seen.=0D - @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D - @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuInit (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_CPU_INIT_TYPE InitType=0D - )=0D -{=0D - return EFI_UNSUPPORTED;=0D -}=0D -=0D -/**=0D - Registers a function to be called from the CPU interrupt handler.=0D -=0D - @param This Protocol instance structure=0D - @param InterruptType Defines which interrupt to hook. IA-32=0D - valid range is 0x00 through 0xFF=0D - @param InterruptHandler A pointer to a function of type=0D - EFI_CPU_INTERRUPT_HANDLER that is called= =0D - when a processor interrupt occurs. A nul= l=0D - pointer is an error condition.=0D -=0D - @retval EFI_SUCCESS If handler installed or uninstalled.=0D - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D - for InterruptType was previously installe= d.=0D - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D - InterruptType was not previously installe= d.=0D - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D - is not supported.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuRegisterInterruptHandler (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D - )=0D -{=0D - return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);=0D -}=0D -=0D -/**=0D - Returns a timer value from one of the CPU's internal timers. There is no= =0D - inherent time interval between ticks but is a function of the CPU freque= ncy.=0D -=0D - @param This - Protocol instance structure.=0D - @param TimerIndex - Specifies which CPU timer is requested.=0D - @param TimerValue - Pointer to the returned timer value.=0D - @param TimerPeriod - A pointer to the amount of time that passe= s=0D - in femtoseconds (10-15) for each increment= =0D - of TimerValue. If TimerValue does not=0D - increment at a predictable rate, then 0 is= =0D - returned. The amount of time that has=0D - passed between two calls to GetTimerValue(= )=0D - can be calculated with the formula=0D - (TimerValue2 - TimerValue1) * TimerPeriod.= =0D - This parameter is optional and may be NULL= .=0D -=0D - @retval EFI_SUCCESS - If the CPU timer count was returned.=0D - @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D - @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D - @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuGetTimerValue (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN UINT32 TimerIndex,=0D - OUT UINT64 *TimerValue,=0D - OUT UINT64 *TimerPeriod OPTIONAL=0D - )=0D -{=0D - if (TimerValue =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - if (TimerIndex !=3D 0) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - *TimerValue =3D (UINT64)RiscVReadMachineTimerInterface ();=0D - if (TimerPeriod !=3D NULL) {=0D - *TimerPeriod =3D DivU64x32 (=0D - 1000000000000000u,=0D - PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D - );=0D - }=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol.=0D -=0D - This function modifies the attributes for the memory region specified by= BaseAddress and=0D - Length from their current attributes to the attributes specified by Attr= ibutes.=0D -=0D - @param This The EFI_CPU_ARCH_PROTOCOL instance.=0D - @param BaseAddress The physical address that is the start address = of a memory region.=0D - @param Length The size in bytes of the memory region.=0D - @param Attributes The bit mask of attributes to set for the memor= y region.=0D -=0D - @retval EFI_SUCCESS The attributes were set for the memory reg= ion.=0D - @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by=0D - BaseAddress and Length cannot be modified.= =0D - @retval EFI_INVALID_PARAMETER Length is zero.=0D - Attributes specified an illegal combinatio= n of attributes that=0D - cannot be set together.=0D - @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of=0D - the memory resource range.=0D - @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory=0D - resource range specified by BaseAddress an= d Length.=0D - The bit mask of attributes is not support = for the memory resource=0D - range specified by BaseAddress and Length.= =0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuSetMemoryAttributes (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D - IN UINT64 Length,=0D - IN UINT64 Attributes=0D - )=0D -{=0D - DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__));=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Initialize the state information for the CPU Architectural Protocol.=0D -=0D - @param ImageHandle Image handle this driver.=0D - @param SystemTable Pointer to the System Table.=0D -=0D - @retval EFI_SUCCESS Thread can be successfully created=0D - @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure=0D - @retval EFI_DEVICE_ERROR Cannot create the thread=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -InitializeCpu (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - //=0D - // Machine mode handler is initiated in CpuExceptionHandlerLibConstructo= r in=0D - // CpuExecptionHandlerLib.=0D - //=0D -=0D - //=0D - // Make sure interrupts are disabled=0D - //=0D - DisableInterrupts ();=0D -=0D - //=0D - // Install CPU Architectural Protocol=0D - //=0D - Status =3D gBS->InstallMultipleProtocolInterfaces (=0D - &mCpuHandle,=0D - &gEfiCpuArchProtocolGuid,=0D - &gCpu,=0D - NULL=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D - return Status;=0D -}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h deleted file mode 100644 index 9d70d7b6..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h +++ /dev/null @@ -1,198 +0,0 @@ -/** @file=0D - RISC-V CPU DXE module header file.=0D -=0D - Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D -=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef CPU_DXE_H_=0D -#define CPU_DXE_H_=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Flush CPU data cache. If the instruction cache is fully coherent=0D - with all DMA operations then function can just return EFI_SUCCESS.=0D -=0D - @param This Protocol instance structure=0D - @param Start Physical address to start flushing from.=0D - @param Length Number of bytes to flush. Round up to chipset= =0D - granularity.=0D - @param FlushType Specifies the type of flush operation to perfo= rm.=0D -=0D - @retval EFI_SUCCESS If cache was flushed=0D - @retval EFI_UNSUPPORTED If flush type is not supported.=0D - @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuFlushCpuDataCache (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS Start,=0D - IN UINT64 Length,=0D - IN EFI_CPU_FLUSH_TYPE FlushType=0D - );=0D -=0D -/**=0D - Enables CPU interrupts.=0D -=0D - @param This Protocol instance structure=0D -=0D - @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D - @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuEnableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D - );=0D -=0D -/**=0D - Disables CPU interrupts.=0D -=0D - @param This Protocol instance structure=0D -=0D - @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D - @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuDisableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D - );=0D -=0D -/**=0D - Return the state of interrupts.=0D -=0D - @param This Protocol instance structure=0D - @param State Pointer to the CPU's current interrupt st= ate=0D -=0D - @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D - @retval EFI_INVALID_PARAMETER State is NULL.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuGetInterruptState (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - OUT BOOLEAN *State=0D - );=0D -=0D -/**=0D - Generates an INIT to the CPU.=0D -=0D - @param This Protocol instance structure=0D - @param InitType Type of CPU INIT to perform=0D -=0D - @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D - seen.=0D - @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D - @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuInit (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_CPU_INIT_TYPE InitType=0D - );=0D -=0D -/**=0D - Registers a function to be called from the CPU interrupt handler.=0D -=0D - @param This Protocol instance structure=0D - @param InterruptType Defines which interrupt to hook. IA-32=0D - valid range is 0x00 through 0xFF=0D - @param InterruptHandler A pointer to a function of type=0D - EFI_CPU_INTERRUPT_HANDLER that is called= =0D - when a processor interrupt occurs. A nul= l=0D - pointer is an error condition.=0D -=0D - @retval EFI_SUCCESS If handler installed or uninstalled.=0D - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D - for InterruptType was previously installe= d.=0D - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D - InterruptType was not previously installe= d.=0D - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D - is not supported.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuRegisterInterruptHandler (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D - );=0D -=0D -/**=0D - Returns a timer value from one of the CPU's internal timers. There is no= =0D - inherent time interval between ticks but is a function of the CPU freque= ncy.=0D -=0D - @param This - Protocol instance structure.=0D - @param TimerIndex - Specifies which CPU timer is requested.=0D - @param TimerValue - Pointer to the returned timer value.=0D - @param TimerPeriod - A pointer to the amount of time that passe= s=0D - in femtoseconds (10-15) for each increment= =0D - of TimerValue. If TimerValue does not=0D - increment at a predictable rate, then 0 is= =0D - returned. The amount of time that has=0D - passed between two calls to GetTimerValue(= )=0D - can be calculated with the formula=0D - (TimerValue2 - TimerValue1) * TimerPeriod.= =0D - This parameter is optional and may be NULL= .=0D -=0D - @retval EFI_SUCCESS - If the CPU timer count was returned.=0D - @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D - @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D - @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuGetTimerValue (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN UINT32 TimerIndex,=0D - OUT UINT64 *TimerValue,=0D - OUT UINT64 *TimerPeriod OPTIONAL=0D - );=0D -=0D -/**=0D - Set memory cacheability attributes for given range of memeory.=0D -=0D - @param This Protocol instance structure=0D - @param BaseAddress Specifies the start address of the=0D - memory range=0D - @param Length Specifies the length of the memory range= =0D - @param Attributes The memory cacheability for the memory ra= nge=0D -=0D - @retval EFI_SUCCESS If the cacheability of that memory range = is=0D - set successfully=0D - @retval EFI_UNSUPPORTED If the desired operation cannot be done=0D - @retval EFI_INVALID_PARAMETER The input parameter is not correct,=0D - such as Length =3D 0=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -CpuSetMemoryAttributes (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D - IN UINT64 Length,=0D - IN UINT64 Attributes=0D - );=0D -=0D -#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Sili= con/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf deleted file mode 100644 index a422c12e..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf +++ /dev/null @@ -1,49 +0,0 @@ -## @file=0D -# RISC-V CPU DXE module.=0D -#=0D -# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x0001001b=0D - BASE_NAME =3D CpuDxe=0D - MODULE_UNI_FILE =3D CpuDxe.uni=0D - FILE_GUID =3D 2AEB1f3E-5B6B-441B-92C1-4A9E6FC85E92= =0D - MODULE_TYPE =3D DXE_DRIVER=0D - VERSION_STRING =3D 1.0=0D -=0D - ENTRY_POINT =3D InitializeCpu=0D -=0D -[Packages]=0D - MdeModulePkg/MdeModulePkg.dec=0D - MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - CpuLib=0D - CpuExceptionHandlerLib=0D - DebugLib=0D - MachineModeTimerLib=0D - RiscVCpuLib=0D - TimerLib=0D - UefiBootServicesTableLib=0D - UefiDriverEntryPoint=0D -=0D -[Sources]=0D - CpuDxe.c=0D - CpuDxe.h=0D -=0D -[Protocols]=0D - gEfiCpuArchProtocolGuid ## PRODUCES=0D -=0D -[Pcd]=0D - gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz=0D -=0D -[Depex]=0D - TRUE=0D -=0D -[UserExtensions.TianoCore."ExtraFiles"]=0D - CpuDxeExtra.uni=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/Sili= con/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni deleted file mode 100644 index 460141a1..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni +++ /dev/null @@ -1,13 +0,0 @@ -// /** @file=0D -//=0D -// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D -//=0D -// SPDX-License-Identifier: BSD-2-Clause-Patent=0D -//=0D -// **/=0D -=0D -=0D -#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V C= PU Architecture Protocol"=0D -=0D -#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver= installs CPU Architecture Protocol."=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b= /Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni deleted file mode 100644 index 6f819f06..00000000 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni +++ /dev/null @@ -1,14 +0,0 @@ -// /** @file=0D -// CpuDxe Localized Strings and Content=0D -//=0D -// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D -//=0D -// SPDX-License-Identifier: BSD-2-Clause-Patent=0D -//=0D -// **/=0D -=0D -#string STR_PROPERTIES_MODULE_NAME=0D -#language en-US=0D -"RISC-V Architectural DXE Driver"=0D -=0D -=0D --=20 2.39.0.windows.2