* [PATCH 1/3] Silicon/RISC-V: Fix build failures caused by duplicated definition
@ 2023-03-11 8:53 Chai, Evan
2023-03-11 8:53 ` [PATCH 2/3] Platform/SiFive: align the library and driver to MdePkg Chai, Evan
2023-03-11 8:53 ` [PATCH 3/3] Platform/SiFive: Fixed build failure casued by wrong alignment Chai, Evan
0 siblings, 2 replies; 3+ messages in thread
From: Chai, Evan @ 2023-03-11 8:53 UTC (permalink / raw)
To: devel; +Cc: Daniel Schaefer, Andrei Warkentin, Sunil V L
Clean up redundant function code becasue they were merged to MdePkg.
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Evan Chai <evan.chai@intel.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/ResetSystemLib/ResetSystemLib.c | 3 +-
.../Library/ResetSystemLib/ResetSystemLib.inf | 3 +-
.../Include/IndustryStandard/RiscV.h | 2 +-
.../Include/Library/RiscVCpuLib.h | 20 +-------
.../Include/Library/RiscVEdk2SbiLib.h | 37 +--------------
.../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 42 +----------------
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 46 +------------------
.../Library/RiscVTimerLib/RiscVTimerLib.c | 2 +
8 files changed, 11 insertions(+), 144 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
index 524b0a63..b4b64421 100644
--- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -2,13 +2,14 @@
Reset System Library functions for RISC-V
Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/DebugLib.h>
#include <Library/ResetSystemLib.h>
-#include <Library/RiscVEdk2SbiLib.h>
+#include <Library/BaseRiscVSbiLib.h>
/**
This function causes a system-wide reset (cold reset), in which
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
index 8987adb9..ff6666f2 100644
--- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -2,6 +2,7 @@
# Library instance for ResetSystem library class for RISC-V using SBI ecalls
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -29,4 +30,4 @@
[LibraryClasses]
DebugLib
- RiscVEdk2SbiLib
+ RiscVSbiLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index 8710aae6..8114766c 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -2,6 +2,7 @@
RISC-V package definitions.
Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -62,7 +63,6 @@
#define RISCV_CSR_MACHINE_MIE 0x304
#define RISCV_CSR_MACHINE_MTVEC 0x305
-#define RISCV_TIMER_COMPARE_BITS 32
//
// Machine Timer and Counter.
//
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index efe85489..f1555843 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -2,6 +2,7 @@
RISC-V CPU library definitions.
Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -96,23 +97,4 @@ RiscVReadMachineImplementId (
VOID
);
-VOID
- RiscVSetSupervisorAddressTranslationRegister (UINT64);
-
-VOID
- RiscVSetSupervisorScratch (UINT64);
-
-UINT64
-RiscVGetSupervisorScratch (
- VOID
- );
-
-VOID
- RiscVSetSupervisorStvec (UINT64);
-
-UINT64
-RiscVGetSupervisorStvec (
- VOID
- );
-
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 36eb16e1..e05e4daa 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -2,6 +2,7 @@
Library to call the RISC-V SBI ecalls
Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -474,42 +475,6 @@ SbiRemoteHfenceVvma (
IN UINTN Size
);
-///
-/// Firmware System Reset (SRST) Extension
-///
-
-/**
- Reset the system
-
- The System Reset Extension provides a function that allow the supervisor
- software to request system-level reboot or shutdown. The term "system" refers
- to the world-view of supervisor software and the underlying SBI
- implementation could be machine mode firmware or hypervisor.
-
- Valid parameters for ResetType and ResetReason are defined in sbi_ecall_interface.h
-
- #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
- #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
- #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
-
- #define SBI_SRST_RESET_REASON_NONE 0x0
- #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
-
- When the call is successful, it will not return.
-
- @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-reset.
- @param[in] ResetReason Why the system resets. No reason or system failure.
- @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is invalid.
- @retval EFI_UNSUPPORTED ResetType is valid but not implemented on the platform.
- @retval EFI_DEVICE_ERROR Unknown error.
-**/
-EFI_STATUS
-EFIAPI
-SbiSystemReset (
- IN UINTN ResetType,
- IN UINTN ResetReason
- );
-
///
/// Vendor Specific extension space: Extension Ids 0x09000000 through 0x09FFFFFF
///
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index e242c9b8..8e27fe2a 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -3,6 +3,7 @@
// RISC-V CPU functions.
//
// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -100,44 +101,3 @@ ASM_FUNC (RiscVReadMachineArchitectureId)
ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
-
-//
-// Set Supervisor mode scratch.
-// @param a0 : Value set to Supervisor mode scratch
-//
-ASM_FUNC (RiscVSetSupervisorScratch)
- csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
- ret
-
-//
-// Get Supervisor mode scratch.
-// @retval a0 : Value in Supervisor mode scratch
-//
-ASM_FUNC (RiscVGetSupervisorScratch)
- csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
- ret
-
-//
-// Set Supervisor mode trap vector.
-// @param a0 : Value set to Supervisor mode trap vector
-//
-ASM_FUNC (RiscVSetSupervisorStvec)
- csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
- ret
-
-//
-// Get Supervisor mode scratch.
-// @retval a0 : Value in Supervisor mode trap vector
-//
-ASM_FUNC (RiscVGetSupervisorStvec)
- csrr a0, RISCV_CSR_SUPERVISOR_STVEC
- ret
-
-//
-// Set Supervisor Address Translation and
-// Protection Register.
-//
-ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
- csrw RISCV_CSR_SUPERVISOR_SATP, a0
- ret
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index a25e16ab..68053a64 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -16,6 +16,7 @@
- SbiLegacyShutdown -> Wait for new System Reset extension
Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -767,51 +768,6 @@ SbiRemoteHFenceVvma (
return TranslateError (Ret.Error);
}
-/**
- Reset the system
-
- The System Reset Extension provides a function that allow the supervisor
- software to request system-level reboot or shutdown. The term "system" refers
- to the world-view of supervisor software and the underlying SBI
- implementation could be machine mode firmware or hypervisor.
-
- Valid parameters for ResetType and ResetReason are defined in sbi_ecall_interface.h
-
- #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
- #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
- #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
-
- #define SBI_SRST_RESET_REASON_NONE 0x0
- #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
-
- When the call is successful, it will not return.
-
- @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-reset.
- @param[in] ResetReason Why the system resets. No reason or system failure.
- @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is invalid.
- @retval EFI_UNSUPPORTED ResetType is valid but not implemented on the platform.
- @retval EFI_DEVICE_ERROR Unknown error.
-**/
-EFI_STATUS
-EFIAPI
-SbiSystemReset (
- IN UINTN ResetType,
- IN UINTN ResetReason
- )
-{
- SBI_RET Ret;
-
- Ret = SbiCall (
- SBI_EXT_SRST,
- SBI_EXT_SRST_RESET,
- 2,
- ResetType,
- ResetReason
- );
-
- return TranslateError (Ret.Error);
-}
-
//
// SBI interface function for the vendor extension
//
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
index 85cd93c5..40a04d60 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -2,6 +2,7 @@
RISC-V instance of Timer Library.
Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -12,6 +13,7 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/RiscVCpuLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
/**
Stalls the CPU for at least the given number of ticks.
--
2.39.0.windows.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/3] Platform/SiFive: align the library and driver to MdePkg
2023-03-11 8:53 [PATCH 1/3] Silicon/RISC-V: Fix build failures caused by duplicated definition Chai, Evan
@ 2023-03-11 8:53 ` Chai, Evan
2023-03-11 8:53 ` [PATCH 3/3] Platform/SiFive: Fixed build failure casued by wrong alignment Chai, Evan
1 sibling, 0 replies; 3+ messages in thread
From: Chai, Evan @ 2023-03-11 8:53 UTC (permalink / raw)
To: devel; +Cc: Daniel Schaefer, Andrei Warkentin, Sunil V L
There are almost same implementation in MdePkg, the part in
platform package can be deprecated.
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Evan Chai <evan.chai@intel.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RiscVTimerLib/BaseRiscVTimerLib.inf | 35 --
.../Library/RiscVTimerLib/RiscVTimerLib.c | 201 ------------
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 13 +-
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 310 ------------------
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 198 -----------
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 49 ---
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.uni | 13 -
| 14 -
8 files changed, 6 insertions(+), 827 deletions(-)
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
delete mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
deleted file mode 100644
index 3c61149d..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ /dev/null
@@ -1,35 +0,0 @@
-## @file
-# RISC-V Timer Library Instance.
-#
-# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = BaseRiscVTimerLib
- FILE_GUID = F0450728-3221-488E-8C63-BD3A8DF500E2
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = TimerLib
-
-[Sources]
- RiscVTimerLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
-
-[Pcd]
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
-
-[LibraryClasses]
- BaseLib
- PcdLib
- RiscVCpuLib
- MachineModeTimerLib
-
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
deleted file mode 100644
index 40a04d60..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/** @file
- RISC-V instance of Timer Library.
-
- Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/RiscVCpuLib.h>
-#include <Register/RiscV64/RiscVImpl.h>
-
-/**
- Stalls the CPU for at least the given number of ticks.
-
- Stalls the CPU for at least the given number of ticks. It's invoked by
- MicroSecondDelay() and NanoSecondDelay().
-
- @param Delay A period of time to delay in ticks.
-
-**/
-VOID
-InternalRiscVTimerDelay (
- IN UINT32 Delay
- )
-{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
- //
- // The target timer count is calculated here
- //
- Ticks = RiscVReadMachineTimerInterface () + Delay;
- Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadMachineTimerInterface ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
- CpuPause ();
- }
- } while (Times-- > 0);
-}
-
-/**
- Stalls the CPU for at least the given number of microseconds.
-
- Stalls the CPU for the number of microseconds specified by MicroSeconds.
-
- @param MicroSeconds The minimum number of microseconds to delay.
-
- @return MicroSeconds
-
-**/
-UINTN
-EFIAPI
-MicroSecondDelay (
- IN UINTN MicroSeconds
- )
-{
- InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- MicroSeconds,
- PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
- ),
- 1000000u
- )
- );
- return MicroSeconds;
-}
-
-/**
- Stalls the CPU for at least the given number of nanoseconds.
-
- Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
-
- @param NanoSeconds The minimum number of nanoseconds to delay.
-
- @return NanoSeconds
-
-**/
-UINTN
-EFIAPI
-NanoSecondDelay (
- IN UINTN NanoSeconds
- )
-{
- InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- NanoSeconds,
- PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
- ),
- 1000000000u
- )
- );
- return NanoSeconds;
-}
-
-/**
- Retrieves the current value of a 64-bit free running performance counter.
-
- Retrieves the current value of a 64-bit free running performance counter. The
- counter can either count up by 1 or count down by 1. If the physical
- performance counter counts by a larger increment, then the counter values
- must be translated. The properties of the counter can be retrieved from
- GetPerformanceCounterProperties().
-
- @return The current value of the free running performance counter.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounter (
- VOID
- )
-{
- return (UINT64)RiscVReadMachineTimerInterface ();
-}
-
-/**return
- Retrieves the 64-bit frequency in Hz and the range of performance counter
- values.
-
- If StartValue is not NULL, then the value that the performance counter starts
- with immediately after is it rolls over is returned in StartValue. If
- EndValue is not NULL, then the value that the performance counter end with
- immediately before it rolls over is returned in EndValue. The 64-bit
- frequency of the performance counter in Hz is always returned. If StartValue
- is less than EndValue, then the performance counter counts up. If StartValue
- is greater than EndValue, then the performance counter counts down. For
- example, a 64-bit free running counter that counts up would have a StartValue
- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
-
- @param StartValue The value the performance counter starts with when it
- rolls over.
- @param EndValue The value that the performance counter ends with before
- it rolls over.
-
- @return The frequency in Hz.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64 *EndValue OPTIONAL
- )
-{
- if (StartValue != NULL) {
- *StartValue = 0;
- }
-
- if (EndValue != NULL) {
- *EndValue = 32 - 1;
- }
-
- return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);
-}
-
-/**
- Converts elapsed ticks of performance counter to time in nanoseconds.
-
- This function converts the elapsed ticks of running performance counter to
- time value in unit of nanoseconds.
-
- @param Ticks The number of elapsed ticks of running performance counter.
-
- @return The elapsed time in nanoseconds.
-
-**/
-UINT64
-EFIAPI
-GetTimeInNanoSecond (
- IN UINT64 Ticks
- )
-{
- UINT64 NanoSeconds;
- UINT32 Remainder;
-
- //
- // Ticks
- // Time = --------- x 1,000,000,000
- // Frequency
- //
- NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u);
-
- //
- // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
- // will not overflow 64-bit.
- //
- NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
-
- return NanoSeconds;
-}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 0591cd6a..b8363c56 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -2,6 +2,7 @@
# RISC-V processor package.
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,11 +40,11 @@
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
- CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
#MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
@@ -81,20 +82,19 @@
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
[LibraryClasses.common.DXE_CORE]
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
[LibraryClasses.common.UEFI_DRIVER]
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
[Components]
- Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -103,7 +103,6 @@
Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
- Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
deleted file mode 100644
index 8d4d406e..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/** @file
- RISC-V CPU DXE driver.
-
- Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "CpuDxe.h"
-
-//
-// Global Variables
-//
-STATIC BOOLEAN mInterruptState = FALSE;
-STATIC EFI_HANDLE mCpuHandle = NULL;
-
-EFI_CPU_ARCH_PROTOCOL gCpu = {
- CpuFlushCpuDataCache,
- CpuEnableInterrupt,
- CpuDisableInterrupt,
- CpuGetInterruptState,
- CpuInit,
- CpuRegisterInterruptHandler,
- CpuGetTimerValue,
- CpuSetMemoryAttributes,
- 1, // NumberOfTimers
- 4 // DmaBufferAlignment
-};
-
-//
-// CPU Arch Protocol Functions
-//
-
-/**
- Flush CPU data cache. If the instruction cache is fully coherent
- with all DMA operations then function can just return EFI_SUCCESS.
-
- @param This Protocol instance structure
- @param Start Physical address to start flushing from.
- @param Length Number of bytes to flush. Round up to chipset
- granularity.
- @param FlushType Specifies the type of flush operation to perform.
-
- @retval EFI_SUCCESS If cache was flushed
- @retval EFI_UNSUPPORTED If flush type is not supported.
- @retval EFI_DEVICE_ERROR If requested range could not be flushed.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuFlushCpuDataCache (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS Start,
- IN UINT64 Length,
- IN EFI_CPU_FLUSH_TYPE FlushType
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Enables CPU interrupts.
-
- @param This Protocol instance structure
-
- @retval EFI_SUCCESS If interrupts were enabled in the CPU
- @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuEnableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
- )
-{
- EnableInterrupts ();
- mInterruptState = TRUE;
- return EFI_SUCCESS;
-}
-
-/**
- Disables CPU interrupts.
-
- @param This Protocol instance structure
-
- @retval EFI_SUCCESS If interrupts were disabled in the CPU.
- @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuDisableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
- )
-{
- DisableInterrupts ();
- mInterruptState = FALSE;
- return EFI_SUCCESS;
-}
-
-/**
- Return the state of interrupts.
-
- @param This Protocol instance structure
- @param State Pointer to the CPU's current interrupt state
-
- @retval EFI_SUCCESS If interrupts were disabled in the CPU.
- @retval EFI_INVALID_PARAMETER State is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuGetInterruptState (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- OUT BOOLEAN *State
- )
-{
- if (State == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- *State = mInterruptState;
- return EFI_SUCCESS;
-}
-
-/**
- Generates an INIT to the CPU.
-
- @param This Protocol instance structure
- @param InitType Type of CPU INIT to perform
-
- @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
- seen.
- @retval EFI_DEVICE_ERROR If CPU INIT failed.
- @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuInit (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_CPU_INIT_TYPE InitType
- )
-{
- return EFI_UNSUPPORTED;
-}
-
-/**
- Registers a function to be called from the CPU interrupt handler.
-
- @param This Protocol instance structure
- @param InterruptType Defines which interrupt to hook. IA-32
- valid range is 0x00 through 0xFF
- @param InterruptHandler A pointer to a function of type
- EFI_CPU_INTERRUPT_HANDLER that is called
- when a processor interrupt occurs. A null
- pointer is an error condition.
-
- @retval EFI_SUCCESS If handler installed or uninstalled.
- @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
- for InterruptType was previously installed.
- @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
- InterruptType was not previously installed.
- @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
- is not supported.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuRegisterInterruptHandler (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
- )
-{
- return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
-}
-
-/**
- Returns a timer value from one of the CPU's internal timers. There is no
- inherent time interval between ticks but is a function of the CPU frequency.
-
- @param This - Protocol instance structure.
- @param TimerIndex - Specifies which CPU timer is requested.
- @param TimerValue - Pointer to the returned timer value.
- @param TimerPeriod - A pointer to the amount of time that passes
- in femtoseconds (10-15) for each increment
- of TimerValue. If TimerValue does not
- increment at a predictable rate, then 0 is
- returned. The amount of time that has
- passed between two calls to GetTimerValue()
- can be calculated with the formula
- (TimerValue2 - TimerValue1) * TimerPeriod.
- This parameter is optional and may be NULL.
-
- @retval EFI_SUCCESS - If the CPU timer count was returned.
- @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
- @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
- @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuGetTimerValue (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN UINT32 TimerIndex,
- OUT UINT64 *TimerValue,
- OUT UINT64 *TimerPeriod OPTIONAL
- )
-{
- if (TimerValue == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (TimerIndex != 0) {
- return EFI_INVALID_PARAMETER;
- }
-
- *TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
- if (TimerPeriod != NULL) {
- *TimerPeriod = DivU64x32 (
- 1000000000000000u,
- PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
- );
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
-
- This function modifies the attributes for the memory region specified by BaseAddress and
- Length from their current attributes to the attributes specified by Attributes.
-
- @param This The EFI_CPU_ARCH_PROTOCOL instance.
- @param BaseAddress The physical address that is the start address of a memory region.
- @param Length The size in bytes of the memory region.
- @param Attributes The bit mask of attributes to set for the memory region.
-
- @retval EFI_SUCCESS The attributes were set for the memory region.
- @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
- BaseAddress and Length cannot be modified.
- @retval EFI_INVALID_PARAMETER Length is zero.
- Attributes specified an illegal combination of attributes that
- cannot be set together.
- @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
- the memory resource range.
- @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
- resource range specified by BaseAddress and Length.
- The bit mask of attributes is not support for the memory resource
- range specified by BaseAddress and Length.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
- )
-{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
- return EFI_SUCCESS;
-}
-
-/**
- Initialize the state information for the CPU Architectural Protocol.
-
- @param ImageHandle Image handle this driver.
- @param SystemTable Pointer to the System Table.
-
- @retval EFI_SUCCESS Thread can be successfully created
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Cannot create the thread
-
-**/
-EFI_STATUS
-EFIAPI
-InitializeCpu (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Machine mode handler is initiated in CpuExceptionHandlerLibConstructor in
- // CpuExecptionHandlerLib.
- //
-
- //
- // Make sure interrupts are disabled
- //
- DisableInterrupts ();
-
- //
- // Install CPU Architectural Protocol
- //
- Status = gBS->InstallMultipleProtocolInterfaces (
- &mCpuHandle,
- &gEfiCpuArchProtocolGuid,
- &gCpu,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
- return Status;
-}
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
deleted file mode 100644
index 9d70d7b6..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/** @file
- RISC-V CPU DXE module header file.
-
- Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef CPU_DXE_H_
-#define CPU_DXE_H_
-
-#include <PiDxe.h>
-
-#include <Protocol/Cpu.h>
-#include <Library/BaseLib.h>
-#include <Library/CpuExceptionHandlerLib.h>
-#include <Library/DebugLib.h>
-#include <Library/RiscVCpuLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-
-/**
- Flush CPU data cache. If the instruction cache is fully coherent
- with all DMA operations then function can just return EFI_SUCCESS.
-
- @param This Protocol instance structure
- @param Start Physical address to start flushing from.
- @param Length Number of bytes to flush. Round up to chipset
- granularity.
- @param FlushType Specifies the type of flush operation to perform.
-
- @retval EFI_SUCCESS If cache was flushed
- @retval EFI_UNSUPPORTED If flush type is not supported.
- @retval EFI_DEVICE_ERROR If requested range could not be flushed.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuFlushCpuDataCache (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS Start,
- IN UINT64 Length,
- IN EFI_CPU_FLUSH_TYPE FlushType
- );
-
-/**
- Enables CPU interrupts.
-
- @param This Protocol instance structure
-
- @retval EFI_SUCCESS If interrupts were enabled in the CPU
- @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuEnableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
- );
-
-/**
- Disables CPU interrupts.
-
- @param This Protocol instance structure
-
- @retval EFI_SUCCESS If interrupts were disabled in the CPU.
- @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuDisableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
- );
-
-/**
- Return the state of interrupts.
-
- @param This Protocol instance structure
- @param State Pointer to the CPU's current interrupt state
-
- @retval EFI_SUCCESS If interrupts were disabled in the CPU.
- @retval EFI_INVALID_PARAMETER State is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuGetInterruptState (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- OUT BOOLEAN *State
- );
-
-/**
- Generates an INIT to the CPU.
-
- @param This Protocol instance structure
- @param InitType Type of CPU INIT to perform
-
- @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
- seen.
- @retval EFI_DEVICE_ERROR If CPU INIT failed.
- @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuInit (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_CPU_INIT_TYPE InitType
- );
-
-/**
- Registers a function to be called from the CPU interrupt handler.
-
- @param This Protocol instance structure
- @param InterruptType Defines which interrupt to hook. IA-32
- valid range is 0x00 through 0xFF
- @param InterruptHandler A pointer to a function of type
- EFI_CPU_INTERRUPT_HANDLER that is called
- when a processor interrupt occurs. A null
- pointer is an error condition.
-
- @retval EFI_SUCCESS If handler installed or uninstalled.
- @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
- for InterruptType was previously installed.
- @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
- InterruptType was not previously installed.
- @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
- is not supported.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuRegisterInterruptHandler (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
- );
-
-/**
- Returns a timer value from one of the CPU's internal timers. There is no
- inherent time interval between ticks but is a function of the CPU frequency.
-
- @param This - Protocol instance structure.
- @param TimerIndex - Specifies which CPU timer is requested.
- @param TimerValue - Pointer to the returned timer value.
- @param TimerPeriod - A pointer to the amount of time that passes
- in femtoseconds (10-15) for each increment
- of TimerValue. If TimerValue does not
- increment at a predictable rate, then 0 is
- returned. The amount of time that has
- passed between two calls to GetTimerValue()
- can be calculated with the formula
- (TimerValue2 - TimerValue1) * TimerPeriod.
- This parameter is optional and may be NULL.
-
- @retval EFI_SUCCESS - If the CPU timer count was returned.
- @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
- @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
- @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-CpuGetTimerValue (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN UINT32 TimerIndex,
- OUT UINT64 *TimerValue,
- OUT UINT64 *TimerPeriod OPTIONAL
- );
-
-/**
- Set memory cacheability attributes for given range of memeory.
-
- @param This Protocol instance structure
- @param BaseAddress Specifies the start address of the
- memory range
- @param Length Specifies the length of the memory range
- @param Attributes The memory cacheability for the memory range
-
- @retval EFI_SUCCESS If the cacheability of that memory range is
- set successfully
- @retval EFI_UNSUPPORTED If the desired operation cannot be done
- @retval EFI_INVALID_PARAMETER The input parameter is not correct,
- such as Length = 0
-
-**/
-EFI_STATUS
-EFIAPI
-CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
- );
-
-#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
deleted file mode 100644
index a422c12e..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+++ /dev/null
@@ -1,49 +0,0 @@
-## @file
-# RISC-V CPU DXE module.
-#
-# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = CpuDxe
- MODULE_UNI_FILE = CpuDxe.uni
- FILE_GUID = 2AEB1f3E-5B6B-441B-92C1-4A9E6FC85E92
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InitializeCpu
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
-
-[LibraryClasses]
- BaseLib
- CpuLib
- CpuExceptionHandlerLib
- DebugLib
- MachineModeTimerLib
- RiscVCpuLib
- TimerLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
-
-[Sources]
- CpuDxe.c
- CpuDxe.h
-
-[Protocols]
- gEfiCpuArchProtocolGuid ## PRODUCES
-
-[Pcd]
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
-
-[Depex]
- TRUE
-
-[UserExtensions.TianoCore."ExtraFiles"]
- CpuDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
deleted file mode 100644
index 460141a1..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
+++ /dev/null
@@ -1,13 +0,0 @@
-// /** @file
-//
-// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-//
-// SPDX-License-Identifier: BSD-2-Clause-Patent
-//
-// **/
-
-
-#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V CPU Architecture Protocol"
-
-#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver installs CPU Architecture Protocol."
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
deleted file mode 100644
index 6f819f06..00000000
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
+++ /dev/null
@@ -1,14 +0,0 @@
-// /** @file
-// CpuDxe Localized Strings and Content
-//
-// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-//
-// SPDX-License-Identifier: BSD-2-Clause-Patent
-//
-// **/
-
-#string STR_PROPERTIES_MODULE_NAME
-#language en-US
-"RISC-V Architectural DXE Driver"
-
-
--
2.39.0.windows.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 3/3] Platform/SiFive: Fixed build failure casued by wrong alignment
2023-03-11 8:53 [PATCH 1/3] Silicon/RISC-V: Fix build failures caused by duplicated definition Chai, Evan
2023-03-11 8:53 ` [PATCH 2/3] Platform/SiFive: align the library and driver to MdePkg Chai, Evan
@ 2023-03-11 8:53 ` Chai, Evan
1 sibling, 0 replies; 3+ messages in thread
From: Chai, Evan @ 2023-03-11 8:53 UTC (permalink / raw)
To: devel; +Cc: Daniel Schaefer, Andrei Warkentin, Sunil V L
The lib and driver should be aligned to Mdepkg.
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Evan Chai <evan.chai@intel.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 15 ++++++++-------
.../U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 2 +-
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 17 +++++++++--------
.../FreedomU540HiFiveUnleashedBoard/U540.fdf | 2 +-
4 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index fc1ed012..372bb8fc 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -2,6 +2,7 @@
# RISC-V EFI on SiFive VC707 (U500) RISC-V platform
#
# Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -150,7 +151,7 @@
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
- CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
# Flattened Device Tree (FDT) access library
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
@@ -228,7 +229,7 @@
RiscVCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
[LibraryClasses.common.DXE_CORE]
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
@@ -245,7 +246,7 @@
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -265,7 +266,7 @@
[LibraryClasses.common.UEFI_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -280,7 +281,7 @@
[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
@@ -300,7 +301,7 @@
[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
!ifdef $(DEBUG_ON_SERIAL_PORT)
@@ -466,7 +467,7 @@
#
# RISC-V Core module
#
- Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
index 4ce19279..da4d3379 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -151,7 +151,7 @@ INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServi
# RISC-V Core Drivers
INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
-INF Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
INF Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index e59955d0..12b08522 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -2,6 +2,7 @@
# RISC-V EFI on SiFive Freedom U540 HiFive Unleashed RISC-V platform
#
# Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -102,6 +103,7 @@
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
+ RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
# RISC-V Platform Library
TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
@@ -152,8 +154,7 @@
RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
#MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
- CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
-
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
# Flattened Device Tree (FDT) access library
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
@@ -230,7 +231,7 @@
RiscVCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
[LibraryClasses.common.DXE_CORE]
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
@@ -247,7 +248,7 @@
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -267,7 +268,7 @@
[LibraryClasses.common.UEFI_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -282,7 +283,7 @@
[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
@@ -302,7 +303,7 @@
[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
!ifdef $(DEBUG_ON_SERIAL_PORT)
@@ -465,7 +466,7 @@
#
# RISC-V Core module
#
- Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
index c58fa635..237ed74a 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
@@ -151,7 +151,7 @@ INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServi
# RISC-V Core Drivers
INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
-INF Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
INF Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
--
2.39.0.windows.2
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2023-03-11 8:53 [PATCH 1/3] Silicon/RISC-V: Fix build failures caused by duplicated definition Chai, Evan
2023-03-11 8:53 ` [PATCH 2/3] Platform/SiFive: align the library and driver to MdePkg Chai, Evan
2023-03-11 8:53 ` [PATCH 3/3] Platform/SiFive: Fixed build failure casued by wrong alignment Chai, Evan
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