From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.41709.1678526077668113171 for ; Sat, 11 Mar 2023 01:14:37 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=BCJeBqbX; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678526077; x=1710062077; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NH8d3k2SNz0a9khJMU9iZBnrF2CcKzA+P3iDBNJYUI8=; b=BCJeBqbXlBK+IfYaUNo0X2Ry53Z+XAuVCHSa608zDBLRCRsZ8CPPmeEc SKgEPYMWR5aWq7ANSuCqVD+LYEJB3QmeLE5DpSWemCgbuEYoVtlDe5HFN F+rtrHxxM4+pEYcOyKYZPGRKEnZQZiaLM0CMHPWDCfc60qQkV2xlCfYT0 HiLyrKRyPn3eu4lUEXHFqWgqgUZLCdsADIyEjucLsY7PH2sDrs8Yim3Uz 8UnNIF9YogBt3Dzz8FtH0KlaA6hTwit011x9nQ+PNlpKOvxFRmr0bPAmK H2YZtH6RmNo/5qyxOTIM/l11/jvVVSjjlyaxuA9cnT2CUtSsJe0Cw4sFX Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="334363889" X-IronPort-AV: E=Sophos;i="5.98,252,1673942400"; d="scan'208";a="334363889" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2023 01:14:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10645"; a="767131487" X-IronPort-AV: E=Sophos;i="5.98,252,1673942400"; d="scan'208";a="767131487" Received: from evanccy.ccr.corp.intel.com ([10.238.200.73]) by FMSMGA003.fm.intel.com with ESMTP; 11 Mar 2023 01:14:35 -0800 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Andrei Warkentin , Sunil V L Subject: [PATCH 1/3] Silicon/RISC-V: Fix build failures caused by duplicated definition Date: Sat, 11 Mar 2023 17:14:30 +0800 Message-Id: <20230311091430.799-1-evan.chai@intel.com> X-Mailer: git-send-email 2.39.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Clean up redundant function code becasue they were merged to MdePkg. Cc: Daniel Schaefer Signed-off-by: Evan Chai Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- .../Library/ResetSystemLib/ResetSystemLib.c | 3 +- .../Library/ResetSystemLib/ResetSystemLib.inf | 3 +- .../Include/IndustryStandard/RiscV.h | 2 +- .../Include/Library/RiscVCpuLib.h | 20 +------- .../Include/Library/RiscVEdk2SbiLib.h | 41 ++--------------- .../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 42 +---------------- .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 46 +------------------ .../Library/RiscVTimerLib/RiscVTimerLib.c | 2 + 8 files changed, 13 insertions(+), 146 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c index 524b0a63..b4b64421 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -2,13 +2,14 @@ Reset System Library functions for RISC-V=0D =0D Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D #include =0D #include =0D -#include =0D +#include =0D =0D /**=0D This function causes a system-wide reset (cold reset), in which=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib= .inf index 8987adb9..ff6666f2 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -2,6 +2,7 @@ # Library instance for ResetSystem library class for RISC-V using SBI eca= lls=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D =0D @@ -29,4 +30,4 @@ =0D [LibraryClasses]=0D DebugLib=0D - RiscVEdk2SbiLib=0D + RiscVSbiLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index 8710aae6..8114766c 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -2,6 +2,7 @@ RISC-V package definitions.=0D =0D Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -62,7 +63,6 @@ #define RISCV_CSR_MACHINE_MIE 0x304=0D #define RISCV_CSR_MACHINE_MTVEC 0x305=0D =0D -#define RISCV_TIMER_COMPARE_BITS 32=0D //=0D // Machine Timer and Counter.=0D //=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index efe85489..f1555843 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -2,6 +2,7 @@ RISC-V CPU library definitions.=0D =0D Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -96,23 +97,4 @@ RiscVReadMachineImplementId ( VOID=0D );=0D =0D -VOID=0D - RiscVSetSupervisorAddressTranslationRegister (UINT64);=0D -=0D -VOID=0D - RiscVSetSupervisorScratch (UINT64);=0D -=0D -UINT64=0D -RiscVGetSupervisorScratch (=0D - VOID=0D - );=0D -=0D -VOID=0D - RiscVSetSupervisorStvec (UINT64);=0D -=0D -UINT64=0D -RiscVGetSupervisorStvec (=0D - VOID=0D - );=0D -=0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h index 36eb16e1..d9369269 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -2,6 +2,7 @@ Library to call the RISC-V SBI ecalls=0D =0D Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -9,8 +10,8 @@ - Hart - Hardware Thread, similar to a CPU core=0D **/=0D =0D -#ifndef RISCV_SBI_LIB_H_=0D -#define RISCV_SBI_LIB_H_=0D +#ifndef RISCV_SBI_LIB2_H_=0D +#define RISCV_SBI_LIB2_H_=0D =0D #include =0D #include =0D @@ -474,42 +475,6 @@ SbiRemoteHfenceVvma ( IN UINTN Size=0D );=0D =0D -///=0D -/// Firmware System Reset (SRST) Extension=0D -///=0D -=0D -/**=0D - Reset the system=0D -=0D - The System Reset Extension provides a function that allow the supervisor= =0D - software to request system-level reboot or shutdown. The term "system" r= efers=0D - to the world-view of supervisor software and the underlying SBI=0D - implementation could be machine mode firmware or hypervisor.=0D -=0D - Valid parameters for ResetType and ResetReason are defined in sbi_ecall_= interface.h=0D -=0D - #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0=0D - #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1=0D - #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2=0D -=0D - #define SBI_SRST_RESET_REASON_NONE 0x0=0D - #define SBI_SRST_RESET_REASON_SYSFAIL 0x1=0D -=0D - When the call is successful, it will not return.=0D -=0D - @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-= reset.=0D - @param[in] ResetReason Why the system resets. No reason or sys= tem failure.=0D - @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is inva= lid.=0D - @retval EFI_UNSUPPORTED ResetType is valid but not implemented = on the platform.=0D - @retval EFI_DEVICE_ERROR Unknown error.=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SbiSystemReset (=0D - IN UINTN ResetType,=0D - IN UINTN ResetReason=0D - );=0D -=0D ///=0D /// Vendor Specific extension space: Extension Ids 0x09000000 through 0x09= FFFFFF=0D ///=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index e242c9b8..8e27fe2a 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -3,6 +3,7 @@ // RISC-V CPU functions.=0D //=0D // Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +// Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -100,44 +101,3 @@ ASM_FUNC (RiscVReadMachineArchitectureId) ASM_FUNC (RiscVReadMachineImplementId)=0D csrr a0, RISCV_CSR_MACHINE_MIMPID=0D ret=0D -=0D -//=0D -// Set Supervisor mode scratch.=0D -// @param a0 : Value set to Supervisor mode scratch=0D -//=0D -ASM_FUNC (RiscVSetSupervisorScratch)=0D - csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0=0D - ret=0D -=0D -//=0D -// Get Supervisor mode scratch.=0D -// @retval a0 : Value in Supervisor mode scratch=0D -//=0D -ASM_FUNC (RiscVGetSupervisorScratch)=0D - csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH=0D - ret=0D -=0D -//=0D -// Set Supervisor mode trap vector.=0D -// @param a0 : Value set to Supervisor mode trap vector=0D -//=0D -ASM_FUNC (RiscVSetSupervisorStvec)=0D - csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0=0D - ret=0D -=0D -//=0D -// Get Supervisor mode scratch.=0D -// @retval a0 : Value in Supervisor mode trap vector=0D -//=0D -ASM_FUNC (RiscVGetSupervisorStvec)=0D - csrr a0, RISCV_CSR_SUPERVISOR_STVEC=0D - ret=0D -=0D -//=0D -// Set Supervisor Address Translation and=0D -// Protection Register.=0D -//=0D -ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)=0D - csrw RISCV_CSR_SUPERVISOR_SATP, a0=0D - ret=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiL= ib.c index a25e16ab..68053a64 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c @@ -16,6 +16,7 @@ - SbiLegacyShutdown -> Wait for new System Reset extension=0D =0D Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @par Revision Reference:=0D @@ -767,51 +768,6 @@ SbiRemoteHFenceVvma ( return TranslateError (Ret.Error);=0D }=0D =0D -/**=0D - Reset the system=0D -=0D - The System Reset Extension provides a function that allow the supervisor= =0D - software to request system-level reboot or shutdown. The term "system" r= efers=0D - to the world-view of supervisor software and the underlying SBI=0D - implementation could be machine mode firmware or hypervisor.=0D -=0D - Valid parameters for ResetType and ResetReason are defined in sbi_ecall_= interface.h=0D -=0D - #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0=0D - #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1=0D - #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2=0D -=0D - #define SBI_SRST_RESET_REASON_NONE 0x0=0D - #define SBI_SRST_RESET_REASON_SYSFAIL 0x1=0D -=0D - When the call is successful, it will not return.=0D -=0D - @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-= reset.=0D - @param[in] ResetReason Why the system resets. No reason or sys= tem failure.=0D - @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is inva= lid.=0D - @retval EFI_UNSUPPORTED ResetType is valid but not implemented = on the platform.=0D - @retval EFI_DEVICE_ERROR Unknown error.=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SbiSystemReset (=0D - IN UINTN ResetType,=0D - IN UINTN ResetReason=0D - )=0D -{=0D - SBI_RET Ret;=0D -=0D - Ret =3D SbiCall (=0D - SBI_EXT_SRST,=0D - SBI_EXT_SRST_RESET,=0D - 2,=0D - ResetType,=0D - ResetReason=0D - );=0D -=0D - return TranslateError (Ret.Error);=0D -}=0D -=0D //=0D // SBI interface function for the vendor extension=0D //=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c index 85cd93c5..40a04d60 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -2,6 +2,7 @@ RISC-V instance of Timer Library.=0D =0D Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -12,6 +13,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D /**=0D Stalls the CPU for at least the given number of ticks.=0D --=20 2.39.0.windows.2