From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.25777.1678727857304579150 for ; Mon, 13 Mar 2023 10:17:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=VxlOclZQ; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BCCC06141D; Mon, 13 Mar 2023 17:17:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1621C4339C; Mon, 13 Mar 2023 17:17:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678727856; bh=9sgliPFeZVL834UJa/X8tTtIOD2c782/yy89sWn3jCY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VxlOclZQRwnJN19Bg/j8yYAHATNGTLPNC8fP72D0Qav3V3w0cY/f3OeDXPKC+72X4 atShu6FW8CyVYH7NYS1GLp9FpUCDgnZZGJF9jmzdKnMO/ae4fRDdBeBd0wetsCpzuC 1lLYSfQG0OTx+b0HjXBdnV3RZF/J5WpoRGMtvRe4dsYTKaqdzZbYDZtYu5n+r0D8QN 0cD0pd0vIea3NdkbodS1eYw+5iUXkjxXvcH8xsCY2tDinzyjYfG8rH+BicEYGlcS/A /RRuJKICcFD41/h0D31SNVYWBSNo2bLeCI99HaAQiUqo6TEq8ySBg21YijByGwTNRd WxzivrY9cbB3Q== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [PATCH v5 01/38] ArmPkg/ArmMmuLib ARM: Remove half baked large page support Date: Mon, 13 Mar 2023 18:16:37 +0100 Message-Id: <20230313171714.3866151-2-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230313171714.3866151-1-ardb@kernel.org> References: <20230313171714.3866151-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Large page support on 32-bit ARM is essentially a glorified contiguous bit where 16 consecutive entries describing a contiguous range with the same attributes are presented in a way that permits the TLB to cache its translation with a single entry. This was never wired up completely, and does not add a lot of value in EFI, where the page granularity is 4k and we expect to be able to set RO and XP permissions on individual pages. Given that large page support complicates the handling of the XN bit at the page level (which is in a different place depending on whether the page is small or large), let's just rip it out. Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 8 ++--- ArmPkg/Include/Chipset/ArmV7Mmu.h | 38 ++++++-------------- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 7 ++-- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 2 +- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 2 +- 5 files changed, 19 insertions(+), 38 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 2daf47ba6fe5..ea856f5cdd26 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -165,7 +165,7 @@ SyncCacheConfigPage ( =0D // Convert SectionAttributes into PageAttributes=0D NextPageAttributes =3D=0D - TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes, 0)= |=0D + TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes) |= =0D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);=0D =0D // obtain page table base=0D @@ -212,7 +212,7 @@ SyncCacheConfigPage ( =0D // Convert back PageAttributes into SectionAttributes=0D *NextSectionAttributes =3D=0D - TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes, 0) = |=0D + TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);=0D =0D return EFI_SUCCESS;=0D @@ -399,7 +399,7 @@ GetMemoryRegionPage ( UINT32 PageDescriptor;=0D =0D // Convert the section attributes into page attributes=0D - PageAttributes =3D ConvertSectionAttributesToPageAttributes (*RegionAttr= ibutes, 0);=0D + PageAttributes =3D ConvertSectionAttributesToPageAttributes (*RegionAttr= ibutes);=0D =0D // Calculate index into first level translation table for start of modif= ication=0D TableIndex =3D ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_D= ESCRIPTOR_PAGE_BASE_SHIFT;=0D @@ -479,7 +479,7 @@ GetMemoryRegion ( ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);=0D =0D PageAttributes =3D PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_A= TTRIBUTE_MASK;=0D - *RegionAttributes =3D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (P= ageAttributes, 0) |=0D + *RegionAttributes =3D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (P= ageAttributes) |=0D TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttribute= s);=0D }=0D =0D diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/Arm= V7Mmu.h index db99527d6efa..7501ebfdf97f 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -98,9 +98,8 @@ #define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))=0D #define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))=0D =0D -#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)=0D -#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)=0D -#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)=0D +#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)=0D +#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)=0D =0D #define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL <= < 12) | (1UL << 3) | (1UL << 2))=0D #define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL <<= 3)=0D @@ -124,30 +123,14 @@ #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6= ) | (1UL << 3) | (1UL << 2))=0D #define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6= ) | (0UL << 3) | (0UL << 2))=0D =0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL= << 12) | (1UL << 3) | (1UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL= << 12) | (0UL << 3) | (0UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL= << 12) | (0UL << 3) | (1UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL= << 12) | (1UL << 3) | (0UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL= << 12) | (1UL << 3) | (1UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL= << 12) | (0UL << 3) | (0UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL= << 12) | (1UL << 3) | (1UL << 2))=0D -#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL= << 12) | (0UL << 3) | (0UL << 2))=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3= << 12)) >> 6) | (Desc & (0x3 << 2)))=0D =0D -#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) (((= (Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)= =0D -#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) (((= (Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)= =0D -#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) (((= (Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)=0D -#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((I= sLargePage)?\=0D - ((((De= sc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MA= SK): \=0D - ((((De= sc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))=0D -#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (Is= LargePage? \=0D - (((Des= c) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CAC= HE_POLICY_MASK): \=0D - (((((D= esc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))=0D -=0D -#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPT= OR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)=0D -=0D -#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) = (IsLargePage? \=0D - (((Des= c) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CAC= HE_POLICY_MASK): \=0D - (((((D= esc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))=0D +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)=0D +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (= 0x3 << 6)) << 6) | (Desc & (0x3 << 2)))=0D =0D #define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MA= SK | TT_DESCRIPTOR_SECTION_NG_MASK | \=0D TT_DESCRIPTOR= _SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \=0D @@ -230,8 +213,7 @@ typedef UINT32 ARM_PAGE_TABLE_ENTRY; =0D UINT32=0D ConvertSectionAttributesToPageAttributes (=0D - IN UINT32 SectionAttributes,=0D - IN BOOLEAN IsLargePage=0D + IN UINT32 SectionAttributes=0D );=0D =0D #endif // ARMV7_MMU_H_=0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Libra= ry/ArmMmuLib/Arm/ArmMmuLibConvert.c index bee8ad7028d3..6e2f08a7ce15 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -15,16 +15,15 @@ =0D UINT32=0D ConvertSectionAttributesToPageAttributes (=0D - IN UINT32 SectionAttributes,=0D - IN BOOLEAN IsLargePage=0D + IN UINT32 SectionAttributes=0D )=0D {=0D UINT32 PageAttributes;=0D =0D PageAttributes =3D 0;=0D - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes, IsLargePage);=0D + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes);=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes)= ;=0D - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes,= IsLargePage);=0D + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes)= ;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes)= ;=0D PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);= =0D =0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 9e304ea05e63..28cc9b2fe058 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -145,7 +145,7 @@ PopulateLevel2PageTable ( );=0D =0D // Translate the Section Descriptor into Page Descriptor=0D - SectionDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionA= ttributesToPageAttributes (*SectionEntry, FALSE);=0D + SectionDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionA= ttributesToPageAttributes (*SectionEntry);=0D =0D BaseSectionAddress =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionE= ntry);=0D =0D diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c index b402197ade99..9ca00c976d5f 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -53,7 +53,7 @@ ConvertSectionToPages ( =0D // Get section attributes and convert to page attributes=0D SectionDescriptor =3D FirstLevelTable[FirstLevelIdx];=0D - PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttri= butesToPageAttributes (SectionDescriptor, FALSE);=0D + PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttri= butesToPageAttributes (SectionDescriptor);=0D =0D // Allocate a page table for the 4KB entries (we use up a full page even= though we only need 1KB)=0D PageTable =3D (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);=0D --=20 2.39.2