From: "duntan" <dun.tan@intel.com>
To: devel@edk2.groups.io
Cc: Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
Rahul Kumar <rahul1.kumar@intel.com>,
Gerd Hoffmann <kraxel@redhat.com>
Subject: [Patch V3 17/18] UefiCpuPkg/CpuPageTableLib: Add check for page table creation
Date: Mon, 20 Mar 2023 13:33:28 +0800 [thread overview]
Message-ID: <20230320053329.410-18-dun.tan@intel.com> (raw)
In-Reply-To: <20230320053329.410-1-dun.tan@intel.com>
Add code to compare ParentPagingEntry Attribute&Mask and input
Attribute&Mask to decide if new next level page table is needed
in non-present ParentPagingEntry condition. This can help avoid
unneccessary page table creation.
For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we
only want to map [1G, 1G+2M] linear address still as non-present.
The expected behaviour should be nothing happens in the process.
However, previous code logic doesn't check if ParentPagingEntry
Attribute&Mask and input Attribute&Mask are the same in non-present
ParentPagingEntry condition. Then a new 4K memory is allocated for
Lv2 since 1G+2M is not 1G-aligned.
So when ParentPagingEntry is non-present, before allocate 4K memory
for next level paging, we also check if ParentPagingEntry Attribute&
Mask and input Attribute&Mask are the same.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
---
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index fbfd6389dc..29191d26b5 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -355,6 +355,24 @@ PageTableLibMapInLevel (
return Status;
}
+ //
+ // Use NOP attributes as the attribute of grand-parents because CPU will consider
+ // the actual attributes of grand-parents when determing the memory type.
+ //
+ PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute);
+ if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
+ == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) &&
+ ( ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0))
+ || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength)
+ == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset))))
+ {
+ //
+ // This function is called when the memory length is less than the region length of the parent level.
+ // No need to split the page when the attributes equal.
+ //
+ return RETURN_SUCCESS;
+ }
+
//
// The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
// It does NOT point to an existing page directory.
--
2.31.1.windows.1
next prev parent reply other threads:[~2023-03-20 5:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 5:33 [Patch V3 00/18] Fix issues in CpuPageTableLib duntan
2023-03-20 5:33 ` [Patch V3 01/18] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition duntan
2023-03-20 5:33 ` [Patch V3 02/18] UefiCpuPkg/CpuPageTableLib: Add check for input Length duntan
2023-03-20 5:33 ` [Patch V3 03/18] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning duntan
2023-03-20 5:33 ` [Patch V3 04/18] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue duntan
2023-03-20 5:33 ` [Patch V3 05/18] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf duntan
2023-03-20 5:33 ` [Patch V3 06/18] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry duntan
2023-03-20 5:33 ` [Patch V3 07/18] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr duntan
2023-03-20 11:42 ` Gerd Hoffmann
2023-03-20 13:58 ` duntan
2023-03-20 5:33 ` [Patch V3 08/18] UefiCpuPkg/CpuPageTableLib: Add manual test to check " duntan
2023-03-20 5:33 ` [Patch V3 09/18] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest duntan
2023-03-20 5:33 ` [Patch V3 10/18] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr duntan
2023-03-20 5:33 ` [Patch V3 11/18] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test duntan
2023-03-20 5:33 ` [Patch V3 12/18] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter duntan
2023-03-20 5:33 ` [Patch V3 13/18] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified duntan
2023-03-20 5:33 ` [Patch V3 14/18] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf duntan
2023-03-20 5:33 ` [Patch V3 15/18] UefiCpuPkg/MpInitLib: Add code to initialize MapMask to 0 duntan
2023-03-20 5:33 ` [Patch V3 16/18] UefiCpuPkg: Modify UnitTest code since tested API is changed duntan
2023-03-20 5:33 ` duntan [this message]
2023-03-20 5:33 ` [Patch V3 18/18] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry duntan
2023-03-20 10:56 ` [edk2-devel] [Patch V3 00/18] Fix issues in CpuPageTableLib Gerd Hoffmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230320053329.410-18-dun.tan@intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox