From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:06 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=aKGWCaJ/; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679290506; x=1710826506; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4+3I9mIU9yHb7Sehm2AabNEzCxOfin9iY3R379PLrXU=; b=aKGWCaJ/n+zryVRjinL77Oui5s4+mBn9N1DleFDpno18cTdmiafl+PjN KZVb/nb/v2PBJVaDSmKnJ/dA9T/qHQu3Ww6XWeHeolUavAI+AuZoIUVmA 50gBxf6ROJOuqWadCKY4EUFGDF2Dzx5hCfVyGhvaE4Cv3YqJy/rVUKufl dZFpJDm/rAHNYKPPZxY9srkIiugvYBB1B4zfCuoc0gUfukxOe9S27MuSj LGCPb9Sv7cdLMZqtjLW+deKEVBM/PvJU/E7T8B8Vghnw1cTLBYs4NxQ3l dp90C4jri79XiORNDN1kAk44rj5IDlTX0ON8vGmu0niz+8pAjlA3a8Nlh w==; X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155770" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155770" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059676" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059676" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:04 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V3 17/18] UefiCpuPkg/CpuPageTableLib: Add check for page table creation Date: Mon, 20 Mar 2023 13:33:28 +0800 Message-Id: <20230320053329.410-18-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index fbfd6389dc..29191d26b5 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -355,6 +355,24 @@ PageTableLibMapInLevel ( return Status; } + // + // Use NOP attributes as the attribute of grand-parents because CPU will consider + // the actual attributes of grand-parents when determing the memory type. + // + PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) + == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && + ( ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength) + == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)))) + { + // + // This function is called when the memory length is less than the region length of the parent level. + // No need to split the page when the attributes equal. + // + return RETURN_SUCCESS; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. -- 2.31.1.windows.1