From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:09 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=hs7/2OPJ; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679290508; x=1710826508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xb4wnsBxbvqEAN56cc9A2hqmANcoqwBASAtrRTm2bNc=; b=hs7/2OPJGnTuNi9elto3krPn2N8M9vN7EHWE1kC3bW6z4893TbEHghEK n0X/BKo2i5ISg5+m/R1hFUX2b9RvUAiEQ6g93l3r2pmENj1zgdJoO9Eao D4TcY0pZsMXltWOtT6ELKn2MO1pgAphbJnW3dIEEzIO/Sgcp+uI9HgQz4 NMe/5In3H/VYMvJ2zy74c/YIhHWTV0hebLmRnuV7bfIcq9BgBFe+lJM7I hr7BhUtHdhc0IKiAHFO0zFqByKxsuOiYZ+hcpXEHqYCiZlvQlfSYScNE2 ysGdrHJ85+/RcSFXWNeex7zSNaSpeBZYBHBWxH2vSRT+E7e0FrY67/Njm g==; X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155796" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155796" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059695" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059695" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:07 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V3 18/18] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Mon, 20 Mar 2023 13:33:29 +0800 Message-Id: <20230320053329.410-19-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Combine the 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 76 ++++++++++++++++++++++------------------------------------------------------ 1 file changed, 22 insertions(+), 54 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 29191d26b5..3e7cc2839f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -345,65 +345,32 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present == 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); - if (RETURN_ERROR (Status)) { - return Status; - } - - // - // Use NOP attributes as the attribute of grand-parents because CPU will consider - // the actual attributes of grand-parents when determing the memory type. - // - PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) - == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && - ( ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) - || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength) - == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)))) - { - // - // This function is called when the memory length is less than the region length of the parent level. - // No need to split the page when the attributes equal. - // - return RETURN_SUCCESS; - } - + if ((ParentPagingEntry->Pce.Present == 0) || IsPle (ParentPagingEntry, Level + 1)) { // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); - CreateNew = TRUE; - *BufferSize -= SIZE_4KB; + OneOfPagingEntry.Pnle.Uint64 = 0; + PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if (Modify) { - ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + if (ParentPagingEntry->Pce.Present == 0) { // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. + // [LinearAddress, LinearAddress + Length] contains non-present range. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask); + Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } } else { - // - // Just make sure Present and MustBeZero (PageSize) bits are accurate. - // - OneOfPagingEntry.Pnle.Uint64 = 0; + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // // Use NOP attributes as the attribute of grand-parents because CPU will consider // the actual attributes of grand-parents when determing the memory type. // - PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && ( ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) @@ -420,17 +387,18 @@ PageTableLibMapInLevel ( ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); CreateNew = TRUE; *BufferSize -= SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask); if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); - for (SubOffset = 0, Index = 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; - SubOffset += RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset = 0, Index = 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; + SubOffset += RegionLength; + } } // -- 2.31.1.windows.1