From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:37 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=e1OvCzw2; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679290477; x=1710826477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G4gx73DQbYtTrLYCktplDcUR1qd9htZM/uqBI5PrZ94=; b=e1OvCzw2n0ZY+DtrTlELWDN0FUpseNobNo3WDqoMtEbgAbvj6tGg8Sor 0XzIeHHgF3SoCY9Bbj5W8QtteQlPJJGirkMMKz0+yT51XNSGlt/rRKhmF m6ax3umbVXrITRJK7z5d2e8zzXy+3cJ3Z917vM4P9agBDeQlZy4D6SIGE lKkVMfECqHKWOoC5NPNKq3K7QcrIt2Jfb4zRBBp1Ti9ikXniE8Jq//vE0 CQXfmjyx2JcBLIXz4Sac2VDd++NvHntR+IMgAuhg6HynAEbh1tPvslg3f 3x69YFdEmYA4CeaWb3erhgNONSjFI4HaU2YBcqbYyn6MOeb0PMyvyALgc w==; X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155493" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155493" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059386" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059386" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:35 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V3 04/18] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Mon, 20 Mar 2023 13:33:15 +0800 Message-Id: <20230320053329.410-5-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index a6414778a7..1f17d8a6d4 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -333,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory type. // PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) - == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) + == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress == 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength) + == (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)))) { // // This function is called when the memory length is less than the region length of the parent level. -- 2.31.1.windows.1