From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30797.1679443043224909338 for ; Tue, 21 Mar 2023 16:57:23 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=UD/y+uVQ; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679443043; x=1710979043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DcorgPdmJm+7YmuICRNycF8WaU677a1M5eoRzNitSPo=; b=UD/y+uVQ48TRvz/UzcVSq7RlmpfYph3vyeIqlBLTyx/XUKGOeo9amS0N CORi/pFmmqysgxWdKPs8JZIc7FXInnX34dfwzAFFMHjuA2w0wICrYpwdf pH9Yx4ofhhSXZJK5Qfnvu8x6oI/XcUklAW+nS+iq/zQGyYNZDym95kQpD hgtPvcH00hiNOBepu+LVFXUTcQZ5YOR7JyhEuw/Zjv72CZGHsRKFLyj/r gxB2hxND5ElaY6QStRBBWFGdTHIPMbKzAHYYqFHd5oqtGjDkNd9vF94oZ NLhulJa3yFG2B/96A//XfNJ7r+UO7WciysKeL+33iktnJ4x4z52NyipiR w==; X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441547" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441547" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627780" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627780" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:57:04 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable case Date: Wed, 22 Mar 2023 07:56:50 +0800 Message-Id: <20230321235650.675-7-ray.ni@intel.com> X-Mailer: git-send-email 2.39.1.windows.1 In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable When TME-MK is enabled, the MtrrLib should substract the TME-MK reserved bits from the max PA returned from CPUID instruction. The new test case guarantees such behavior in MtrrLib. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani --- .../MtrrLib/UnitTest/MtrrLibUnitTest.c | 18 +-- .../MtrrLib/UnitTest/MtrrLibUnitTest.h | 3 +- UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 119 ++++++++++++++---- 3 files changed, 107 insertions(+), 33 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c index b9a97dee09..1409ae27bb 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c @@ -1,7 +1,7 @@ /** @file=0D Unit tests of the MtrrLib instance of the MtrrLib class=0D =0D - Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -30,6 +30,8 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] =3D= { { 48, TRUE, TRUE, CacheWriteThrough, 12 },=0D { 48, TRUE, TRUE, CacheWriteProtected, 12 },=0D { 48, TRUE, TRUE, CacheWriteCombining, 12 },=0D +=0D + { 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME=0D };=0D =0D UINT32 mFixedMtrrsIndex[] =3D {=0D @@ -219,7 +221,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( &WcCount=0D );=0D GenerateValidAndConfigurableMtrrPairs (=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits= ,=0D RawMtrrRange,=0D UcCount,=0D WtCount,=0D @@ -232,7 +234,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges);=0D GetEffectiveMemoryRanges (=0D SystemParameter->DefaultCacheType,=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits= ,=0D RawMtrrRange,=0D ExpectedVariableMtrrUsage,=0D ExpectedMemoryRanges,=0D @@ -278,7 +280,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges);=0D CollectTestResult (=0D SystemParameter->DefaultCacheType,=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts,=0D SystemParameter->VariableMtrrCount,=0D &LocalMtrrs,=0D ActualMemoryRanges,=0D @@ -325,7 +327,7 @@ UnitTestInvalidMemoryLayouts ( SystemParameter =3D (MTRR_LIB_SYSTEM_PARAMETER *)Context;=0D =0D RangeCount =3D Random32 (1, ARRAY_SIZE (Ranges));=0D - MaxAddress =3D 1ull << SystemParameter->PhysicalAddressBits;=0D + MaxAddress =3D 1ull << (SystemParameter->PhysicalAddressBits - SystemPar= ameter->MkTmeKeyidBits);=0D =0D for (Index =3D 0; Index < RangeCount; Index++) {=0D do {=0D @@ -967,7 +969,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( &WcCount=0D );=0D GenerateValidAndConfigurableMtrrPairs (=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits= ,=0D RawMtrrRange,=0D UcCount,=0D WtCount,=0D @@ -980,7 +982,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges);=0D GetEffectiveMemoryRanges (=0D SystemParameter->DefaultCacheType,=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits= ,=0D RawMtrrRange,=0D ExpectedVariableMtrrUsage,=0D ExpectedMemoryRanges,=0D @@ -1019,7 +1021,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges);=0D CollectTestResult (=0D SystemParameter->DefaultCacheType,=0D - SystemParameter->PhysicalAddressBits,=0D + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts,=0D SystemParameter->VariableMtrrCount,=0D &LocalMtrrs,=0D ActualMemoryRanges,=0D diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h index 57e656c555..4471c1dcf7 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h @@ -1,6 +1,6 @@ /** @file=0D =0D - Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -40,6 +40,7 @@ typedef struct { BOOLEAN FixedMtrrSupported;=0D MTRR_MEMORY_CACHE_TYPE DefaultCacheType;=0D UINT32 VariableMtrrCount;=0D + UINT8 MkTmeKeyidBits;=0D } MTRR_LIB_SYSTEM_PARAMETER;=0D =0D extern UINT32 mFixedMtrrsIndex[];=0D diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Lib= rary/MtrrLib/UnitTest/Support.c index 260966e7b6..ba1de10034 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -12,13 +12,15 @@ MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] =3D { CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProt= ected, CacheWriteBack=0D };=0D =0D -UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTR= R];=0D -MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VAR= IABLE_MTRR];=0D -MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_NUMBER_OF_VAR= IABLE_MTRR];=0D -MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr;=0D -MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr;=0D -CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx;=0D -CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax;=0D +UINT64 mFixedMtrrsValue[MTRR_NUMBER_= OF_FIXED_MTRR];=0D +MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_N= UMBER_OF_VARIABLE_MTRR];=0D +MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_N= UMBER_OF_VARIABLE_MTRR];=0D +MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr;=0D +MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr;=0D +MSR_IA32_TME_ACTIVATE_REGISTER mTmeActivateMsr;=0D +CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx;=0D +CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX mCpuidExtendedFeatureFlagsEcx= ;=0D +CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax;=0D =0D BOOLEAN mRandomInput;=0D UINTN mNumberIndex =3D 0;=0D @@ -87,34 +89,42 @@ GenerateRandomNumbers ( }=0D =0D /**=0D - Retrieves CPUID information.=0D + Retrieves CPUID information using an extended leaf identifier.=0D +=0D + Executes the CPUID instruction with EAX set to the value specified by In= dex=0D + and ECX set to the value specified by SubIndex. This function always ret= urns=0D + Index. This function is only available on IA-32 and x64.=0D =0D - Executes the CPUID instruction with EAX set to the value specified by In= dex.=0D - This function always returns Index.=0D If Eax is not NULL, then the value of EAX after CPUID is returned in Eax= .=0D If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx= .=0D If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx= .=0D If Edx is not NULL, then the value of EDX after CPUID is returned in Edx= .=0D - This function is only available on IA-32 and x64.=0D =0D - @param Index The 32-bit value to load into EAX prior to invoking the CP= UID=0D - instruction.=0D - @param Eax The pointer to the 32-bit EAX value returned by the CPUID= =0D - instruction. This is an optional parameter that may be NUL= L.=0D - @param Ebx The pointer to the 32-bit EBX value returned by the CPUID= =0D - instruction. This is an optional parameter that may be NUL= L.=0D - @param Ecx The pointer to the 32-bit ECX value returned by the CPUID= =0D - instruction. This is an optional parameter that may be NUL= L.=0D - @param Edx The pointer to the 32-bit EDX value returned by the CPUID= =0D - instruction. This is an optional parameter that may be NUL= L.=0D + @param Index The 32-bit value to load into EAX prior to invoking th= e=0D + CPUID instruction.=0D + @param SubIndex The 32-bit value to load into ECX prior to invoking th= e=0D + CPUID instruction.=0D + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID=0D + instruction. This is an optional parameter that may be= =0D + NULL.=0D + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID=0D + instruction. This is an optional parameter that may be= =0D + NULL.=0D + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID=0D + instruction. This is an optional parameter that may be= =0D + NULL.=0D + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID=0D + instruction. This is an optional parameter that may be= =0D + NULL.=0D =0D @return Index.=0D =0D **/=0D UINT32=0D EFIAPI=0D -UnitTestMtrrLibAsmCpuid (=0D +UnitTestMtrrLibAsmCpuidEx (=0D IN UINT32 Index,=0D + IN UINT32 SubIndex,=0D OUT UINT32 *Eax OPTIONAL,=0D OUT UINT32 *Ebx OPTIONAL,=0D OUT UINT32 *Ecx OPTIONAL,=0D @@ -124,7 +134,7 @@ UnitTestMtrrLibAsmCpuid ( switch (Index) {=0D case CPUID_SIGNATURE:=0D if (Eax !=3D NULL) {=0D - *Eax =3D CPUID_VERSION_INFO;=0D + *Eax =3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS;=0D }=0D =0D return Index;=0D @@ -134,6 +144,13 @@ UnitTestMtrrLibAsmCpuid ( *Edx =3D mCpuidVersionInfoEdx.Uint32;=0D }=0D =0D + return Index;=0D + break;=0D + case CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS:=0D + if (Ecx !=3D NULL) {=0D + *Ecx =3D mCpuidExtendedFeatureFlagsEcx.Uint32;=0D + }=0D +=0D return Index;=0D break;=0D case CPUID_EXTENDED_FUNCTION:=0D @@ -159,6 +176,44 @@ UnitTestMtrrLibAsmCpuid ( return Index;=0D }=0D =0D +/**=0D + Retrieves CPUID information.=0D +=0D + Executes the CPUID instruction with EAX set to the value specified by In= dex.=0D + This function always returns Index.=0D + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax= .=0D + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx= .=0D + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx= .=0D + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx= .=0D + This function is only available on IA-32 and x64.=0D +=0D + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID=0D + instruction.=0D + @param Eax The pointer to the 32-bit EAX value returned by the CPUID= =0D + instruction. This is an optional parameter that may be NUL= L.=0D + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID= =0D + instruction. This is an optional parameter that may be NUL= L.=0D + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID= =0D + instruction. This is an optional parameter that may be NUL= L.=0D + @param Edx The pointer to the 32-bit EDX value returned by the CPUID= =0D + instruction. This is an optional parameter that may be NUL= L.=0D +=0D + @return Index.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +UnitTestMtrrLibAsmCpuid (=0D + IN UINT32 Index,=0D + OUT UINT32 *Eax OPTIONAL,=0D + OUT UINT32 *Ebx OPTIONAL,=0D + OUT UINT32 *Ecx OPTIONAL,=0D + OUT UINT32 *Edx OPTIONAL=0D + )=0D +{=0D + return UnitTestMtrrLibAsmCpuidEx (Index, 0, Eax, Ebx, Ecx, Edx);=0D +}=0D +=0D /**=0D Returns a 64-bit Machine Specific Register(MSR).=0D =0D @@ -207,6 +262,10 @@ UnitTestMtrrLibAsmReadMsr64 ( return mMtrrCapMsr.Uint64;=0D }=0D =0D + if (MsrIndex =3D=3D MSR_IA32_TME_ACTIVATE) {=0D + return mTmeActivateMsr.Uint64;=0D + }=0D +=0D //=0D // Should never fall through to here=0D //=0D @@ -324,10 +383,22 @@ InitializeMtrrRegs ( //=0D // Hook BaseLib functions used by MtrrLib that require some emulation.=0D //=0D - gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid;=0D + gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid;=0D + gUnitTestHostBaseLib.X86->AsmCpuidEx =3D UnitTestMtrrLibAsmCpuidEx;=0D +=0D gUnitTestHostBaseLib.X86->AsmReadMsr64 =3D UnitTestMtrrLibAsmReadMsr64;= =0D gUnitTestHostBaseLib.X86->AsmWriteMsr64 =3D UnitTestMtrrLibAsmWriteMsr64= ;=0D =0D + if (SystemParameter->MkTmeKeyidBits !=3D 0) {=0D + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 1;=0D + mTmeActivateMsr.Bits.TmeEnable =3D 1;=0D + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D SystemParameter->MkTmeKe= yidBits;=0D + } else {=0D + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 0;=0D + mTmeActivateMsr.Bits.TmeEnable =3D 0;=0D + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D 0;=0D + }=0D +=0D return UNIT_TEST_PASSED;=0D }=0D =0D --=20 2.39.1.windows.1