From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:56 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=FRPYlefL; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679557316; x=1711093316; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p+mAMgGllwRfVvRQZLECnk9B1oIL5QMcPP6GDLCYkg8=; b=FRPYlefL6bBc6EQn5eisKTb1PdlLg734eV6Tb126uN8k2DFOsLCTH2UA gC0lPIWZjxewCOoIyKEDxnhOoMAzQMzGsyGi0L1koOeFFAQoFksvUIurq j08SV1t2t4IAGn8rqAYDh4IgC+vC1mX6NYlPPXmMkXVlkMep8jBMeuFf7 aj+LwsGnxT+7Ohk2Wa/rtFvZa4OpXk4/hHSZkyOj99T0z9n+Y/MlhtraD 8huBYwFumGm0Sx/htmCf2haGrBr2/kMT8ahhTyC1R8jrSuqLOPafIHo6t OUPDwY3SNOsthzKCHB2wURkrTLURmOY/gKPwpShS5b3/mgEaY7pi1/mQh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699856" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699856" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616891" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616891" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:54 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V4 18/21] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Thu, 23 Mar 2023 15:40:54 +0800 Message-Id: <20230323074057.549-19-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 83 +++++++++++++++++++++++++++++++---------------------------------------------------- 1 file changed, 31 insertions(+), 52 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 55a756ad90..773948349e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -348,68 +348,45 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present == 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); - if (RETURN_ERROR (Status)) { - return Status; - } - + if ((ParentPagingEntry->Pce.Present == 0) || IsPle (ParentPagingEntry, Level + 1)) { // - // Check the attribute in ParentPagingEntry is equal to attribute calculated by input Attribue and Mask. - // - PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) - == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) - { - return RETURN_SUCCESS; - } - - // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); - CreateNew = TRUE; - *BufferSize -= SIZE_4KB; + OneOfPagingEntry.Pnle.Uint64 = 0; + PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); - if (Modify) { - ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + if (ParentPagingEntry->Pce.Present == 0) { // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. + // [LinearAddress, LinearAddress + Length] contains non-present range. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask); + Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } } else { - // - // Just make sure Present and MustBeZero (PageSize) bits are accurate. - // - OneOfPagingEntry.Pnle.Uint64 = 0; + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // - // Use NOP attributes as the attribute of grand-parents because CPU will consider - // the actual attributes of grand-parents when determing the memory type. + // Check if the attribute, the physical address calculated by ParentPagingEntry is equal to + // the attribute, the physical address calculated by input Attribue and Mask. // - PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute); if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) { - // - // This function is called when the memory length is less than the region length of the parent level. - // No need to split the page when the attributes equal. - // if ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) { return RETURN_SUCCESS; } + // + // Non-present entry won't reach there since: + // 1.When map non-present entry to present, the attribute must be different. + // 2.When still map non-present entry to non-present, PageTableBaseAddressLow and High in Mask must be 0. + // + ASSERT (ParentPagingEntry->Pce.Present == 1); PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + PagingEntryIndex * RegionLength; PhysicalAddrInAttr = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & (~RegionMask); if (PhysicalAddrInEntry == PhysicalAddrInAttr) { @@ -420,17 +397,19 @@ PageTableLibMapInLevel ( ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); CreateNew = TRUE; *BufferSize -= SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask); + if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); - for (SubOffset = 0, Index = 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; - SubOffset += RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset = 0, Index = 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; + SubOffset += RegionLength; + } } // -- 2.31.1.windows.1