From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:27 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=fpICoLCS; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679557287; x=1711093287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hic1Tmv8K8mM8Al4OZUcK+Y78BKVHMXGDd06LwFn9Ag=; b=fpICoLCSCx/yHj43Rz96CcCyDl3QztPlAHDr3wnk3mk8A+ZMScF24vNa qWGwoMLKTM/svce7X6Xcw0D2xg+sn1U2vdDG7+/bVZrJC9AOuLLQshFaZ 1Tl2NZgAP6zAxWXkhyvgzp/ipfqC3KeYhb5UqotU9Qwdhd8QkfUIeYs2L Inczty6Y2Ny6YpiEpRoRPCw+Re9Dlga/GdMfsdYYwlgCVT4j4mj4VlTVY 608p591w+CzuszN3NEY0pDaUQ14Ow5/v+fIzzwSKK8MG1DwmaFJY8c9MB t/TmyFIp7Qll2L6MYV1ft9BM+CmgsPMbG3FwQr3kS6uo/urZzUaopRPh9 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699621" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699621" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616838" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616838" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:26 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr Date: Thu, 23 Mar 2023 15:40:44 +0800 Message-Id: <20230323074057.549-9-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 2 +- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 78 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Include/Library/CpuPageTableLib.h index 5f44ece548..6bda15b5bc 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -76,7 +76,7 @@ typedef enum { @param[in] Mask The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0. @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table creation/updating. BufferSize is updated to indicate the expected buffer size. diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 76febdd42d..2ad22b333d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -215,6 +215,43 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled = 0; } +/** + Check if the combination for Attribute and Mask is valid for non-present entry. + 1.Mask.Present is 0 but some other attributes is provided. This case should be invalid. + 2.Map non-present range to present. In this case, all attributes should be provided. + + @param[in] Attribute The attribute of the linear address range. + @param[in] Mask The mask used for attribute to check. + + @retval RETURN_INVALID_PARAMETER The combination for Attribute and Mask is invalid. + @retval RETURN_SUCCESS The combination for Attribute and Mask is valid. +**/ +RETURN_STATUS +IsAttributesAndMaskValidForNonPresentEntry ( + IN IA32_MAP_ATTRIBUTE *Attribute, + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Mask->Bits.Present == 1) && (Attribute->Bits.Present == 1)) { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || (Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) || + (Mask->Bits.Accessed == 0) || (Mask->Bits.Dirty == 0) || (Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) || + (Mask->Bits.PageTableBaseAddress == 0) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0)) + { + return RETURN_INVALID_PARAMETER; + } + } else if ((Mask->Bits.Present == 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitted. + // + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with specified attribute in the specified level. @@ -237,6 +274,7 @@ PageTableLibSetPnle ( when a new physical base address is set. @param[in] Mask The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0. + @retval RETURN_INVALID_PARAMETER The combination of Attribute and Mask for non-present entry is invalid. @retval RETURN_SUCCESS PageTable is created/updated successfully. **/ RETURN_STATUS @@ -260,6 +298,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexEnd; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -306,6 +345,14 @@ PageTableLibMapInLevel ( // if (ParentPagingEntry->Pce.Present == 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present range. + // + Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -380,6 +427,27 @@ PageTableLibMapInLevel ( ParentPagingEntry->Uint64 = ((UINTN)(VOID *)PagingEntry) | (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { + // + // If (LinearAddress + Length - 1) is not in the same ParentPagingEntry with (LinearAddress + Offset), then the remaining child PagingEntry + // starting from PagingEntryIndex of ParentPagingEntry is all covered by [LinearAddress + Offset, LinearAddress + Length - 1]. + // + PagingEntryIndexEnd = (BitFieldRead64 (LinearAddress + Length - 1, BitStart + 9, 63) != BitFieldRead64 (LinearAddress + Offset, BitStart + 9, 63)) ? 511 : + (UINTN)BitFieldRead64 (LinearAddress + Length - 1, BitStart, BitStart + 9 - 1); + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); + for (Index = PagingEntryIndex; Index <= PagingEntryIndexEnd; Index++) { + if (PagingEntry[Index].Pce.Present == 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present range. + // + Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -427,7 +495,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited from parent. // e.g.: Set PDE[0-255].ReadWrite = 0 // - PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index = 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present == 0) { continue; @@ -553,7 +620,7 @@ PageTableLibMapInLevel ( @param[in] Mask The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0. @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table creation/updating. BufferSize is updated to indicate the expected buffer size. @@ -615,6 +682,14 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } + // + // If to map [LinearAddress, LinearAddress + Length] as non-present, + // all attributes except Present should not be provided. + // + if ((Attribute->Bits.Present == 0) && (Mask->Bits.Present == 1) && (Mask->Uint64 > 1)) { + return RETURN_INVALID_PARAMETER; + } + MaxLeafLevel = (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel = (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); MaxLinearAddress = LShiftU64 (1, 12 + MaxLevel * 9); -- 2.31.1.windows.1