From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.96113.1679647930408970241 for ; Fri, 24 Mar 2023 01:52:13 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=C+QmvhE9; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679647933; x=1711183933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YGpmOp6WnJ1pUdlHV8MYhJkfh+XGYU6K1v2UBt+4CG8=; b=C+QmvhE9JA9FhEshWhCk8bxTh2+4jr4BBhDY3XIHPGBZ0xwDXAcPMaXs O4K7mqVj8UQTn3KeUdCjI+WCxrIQ40XHeNKlz7tA7QvY7WYeQAWm+a7uH v86xbPX+m5DRc+5WHw0pawPhitvglp3Eg2MFfvGCAjiJTmz6BsbAYFrHl b3UneufgGkh0tnT289e4RERhIf0uOqEHq7HVCIP/mpK8A8J0F+wTltLmL OBHn3k0b/HSM/JKeP2XKm6/waGVtbX64DdJ43fnL5WSri0ngHMRs3QcDx V6aXjo5U556OLZUq9h8SDMiw4Adf5bq/jyoFnJ7EKzYHs03J/kghbqP6I w==; X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="323603772" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="323603772" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 01:52:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="713010791" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="713010791" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 01:52:11 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V6 04/22] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Fri, 24 Mar 2023 16:51:50 +0800 Message-Id: <20230324085151.1237-2-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230324085151.1237-1-dun.tan@intel.com> References: <20230324085151.1237-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 127b65183f..b94ef07c56 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -274,6 +274,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildMask; IA32_MAP_ATTRIBUTE CurrentMask; IA32_MAP_ATTRIBUTE LocalParentAttribute; + UINT64 PhysicalAddrInEntry; + UINT64 PhysicalAddrInAttr; ASSERT (Level != 0); ASSERT ((Attribute != NULL) && (Mask != NULL)); @@ -341,7 +343,15 @@ PageTableLibMapInLevel ( // This function is called when the memory length is less than the region length of the parent level. // No need to split the page when the attributes equal. // - return RETURN_SUCCESS; + if (Mask->Bits.PageTableBaseAddress == 0) { + return RETURN_SUCCESS; + } + + PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + MultU64x32 (RegionLength, (UINT32)PagingEntryIndex); + PhysicalAddrInAttr = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & (~RegionMask); + if (PhysicalAddrInEntry == PhysicalAddrInAttr) { + return RETURN_SUCCESS; + } } ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); -- 2.31.1.windows.1