From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.96113.1679647930408970241 for ; Fri, 24 Mar 2023 01:52:16 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=CoTKPmUa; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679647936; x=1711183936; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u7RTG52Ap2gecEex9Au7fjgH46Zaz4cwLZnt2ohWYVk=; b=CoTKPmUaqznOhwFZRoUjcZRge9kF4C9LwsXTr+c1MDPD7lyQu++hnRK5 Ev077e2wMjva9rek9XUVvRJiMO5nnY1DEBPXAqTpNfZ2sI53T+CyzDfaP JzpYol7AgI7uVvGTVr1Bb0q40hEsBJ0nd9l7qIV+w/TuA+XyWIdv1fwvk GtHq/aINDP3bgtOUgk4EAqoFZhvc7fw6mBJltj5V4cRTLqq9sWR+k/ete F4wWFqosTajqrwdQIkJ5aXl44Nz65VwuBWy2ZKoS/vNglRY3eG+BzSfWs fKwVGv3gSFu6NtXRhyjNcRNh4Hlm7cd7tZ/bLf+g43I2qZOsyBu2sPdL0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="323603796" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="323603796" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 01:52:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="713010796" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="713010796" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 01:52:14 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V6 06/22] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry Date: Fri, 24 Mar 2023 16:51:51 +0800 Message-Id: <20230324085151.1237-3-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230324085151.1237-1-dun.tan@intel.com> References: <20230324085151.1237-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 57f1db203b..f09bb63ad1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -363,21 +363,24 @@ PageTableLibMapInLevel ( // // Create 512 child-level entries that map to 2M/4K. // - ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); + ZeroMem (PagingEntry, SIZE_4KB); + + for (SubOffset = 0, Index = 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; + SubOffset += RegionLength; + } // // Set NOP attributes // Note: Should NOT inherit the attributes from the original entry because a zero RW bit // will make the entire region read-only even the child entries set the RW bit. // + // Non-leaf entry doesn't have PAT bit. So use ~IA32_PE_BASE_ADDRESS_MASK_40 is to make sure PAT bit + // (bit12) in original big-leaf entry is not assigned to PageTableBaseAddress field of non-leaf entry. + // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask); - - PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle); - for (SubOffset = 0, Index = 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset; - SubOffset += RegionLength; - } + ParentPagingEntry->Uint64 = ((UINTN)(VOID *)PagingEntry) | (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { // -- 2.31.1.windows.1