From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.98508.1679655856505148087 for ; Fri, 24 Mar 2023 04:04:16 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: vivek.gautam@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39B7011FB; Fri, 24 Mar 2023 04:05:00 -0700 (PDT) Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3B1843F6C4; Fri, 24 Mar 2023 04:03:57 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com Subject: [edk2-platforms][PATCH V3 4/5] Platform/Sgi: Initialize additional UART controllers Date: Fri, 24 Mar 2023 16:33:02 +0530 Message-Id: <20230324110303.1168851-5-vivek.gautam@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Shriram K The IO virtualization block on reference design platforms allow connecting SoC expansion devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by: Shriram K Signed-off-by: Vivek Gautam --- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 9 ++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 6 +- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 64 ++++++++++= +++++++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 44 ++++++++++= +++- 4 files changed, 116 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Pl= atform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf index 9d89314a594e..3cd7e2329c22 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,6 +17,7 @@ VirtioDevices.c =20 [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec @@ -37,10 +38,16 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetSupported =20 [FixedPcd] + gArmSgiTokenSpaceGuid.PcdChipCount + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioBlkSize gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize =20 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + [Depex] TRUE diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Pl= atform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index 1ca7679b4191..020bde0d1f56 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,10 +41,12 @@ gArmPlatformTokenSpaceGuid.PcdCoreCount gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase =20 - gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdDramBlock2Base gArmSgiTokenSpaceGuid.PcdDramBlock2Size gArmSgiTokenSpaceGuid.PcdGicSize + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip =20 gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Plat= form/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c index 2f72e7152ff3..b3a998bc1585 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -9,6 +9,9 @@ #include #include #include +#include + +#include #include =20 VOID @@ -16,6 +19,64 @@ InitVirtioDevices ( VOID ); =20 +/** + Initialize UART controllers connected to IO Virtualization block. + + Use PL011UartLib Library to initialize UART controllers that are prese= nt in + the SoC expansion block. This SoC expansion block is connected to the = IO + virtualization block on Arm infrastructure reference design (RD) platf= orms. + + @retval None +**/ +STATIC +VOID +InitIoVirtSocExpBlkUartControllers (VOID) +{ + EFI_STATUS Status; + EFI_PARITY_TYPE Parity; + EFI_STOP_BITS_TYPE StopBits; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + UINT8 DataBits; + UINT8 UartIdx; + UINT32 ChipIdx; + UINT64 UartAddr; + + if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 0) + return; + + ReceiveFifoDepth =3D 0; + Parity =3D 1; + DataBits =3D 8; + StopBits =3D 1; + BaudRate =3D 115200; + + for (ChipIdx =3D 0; ChipIdx < FixedPcdGet32 (PcdChipCount); ChipIdx++)= { + for (UartIdx =3D 0; UartIdx < 2; UartIdx++) { + UartAddr =3D SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(Uart= Idx); + + Status =3D PL011UartInitializePort ( + (UINTN)UartAddr, + FixedPcdGet32 (PcdSerialDbgUartClkInHz), + &BaudRate, + &ReceiveFifoDepth, + &Parity, + &DataBits, + &StopBits + ); + + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Failed to init PL011_UART%u on IO Virt Block port, status: %r= \n", + UartIdx, + Status + )); + } + } + } +} + EFI_STATUS EFIAPI ArmSgiPkgEntryPoint ( @@ -32,6 +93,7 @@ ArmSgiPkgEntryPoint ( } =20 InitVirtioDevices (); + InitIoVirtSocExpBlkUartControllers (); =20 return Status; } diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/P= latform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index 8139b75d8ee4..fa3cfbc730f6 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* Copyright (c) 2018-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -13,11 +13,24 @@ #include #include =20 +#include #include =20 // Total number of descriptors, including the final "end-of-table" descr= iptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \ - (14 + (FixedPcdGet32 (PcdChipCount) * 2)) +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS = \ + ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + = \ + (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * = \ + FixedPcdGet32 (PcdChipCount) * 2)) + +// Memory Map descriptor for IO Virtualization SoC Expansion Block UART +#define IO_VIRT_SOC_EXP_BLK_UART_MMAP(UartIdx, ChipIdx) = \ + VirtualMemoryTable[++Index].PhysicalBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].VirtualBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].Length =3D SIZE_64KB; = \ + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; + =20 /** Returns the Virtual Memory Map of the platform. @@ -171,6 +184,31 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D SIZE_64KB; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; =20 +#if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 1) + // Chip-0 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 0) + // Chip-0 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 0) +#if (FixedPcdGet32 (PcdChipCount) > 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 1) +#if (FixedPcdGet32 (PcdChipCount) > 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 2) +#if (FixedPcdGet32 (PcdChipCount) > 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 3) +#endif +#endif +#endif +#endif + // DDR - (2GB - 16MB) VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemor= yBase); VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemor= yBase); --=20 2.25.1