From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mx.groups.io with SMTP id smtpd.web10.105577.1679672629359329183 for ; Fri, 24 Mar 2023 08:43:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=l9JmMNDQ; spf=pass (domain: rivosinc.com, ip: 209.85.214.174, mailfrom: dhaval@rivosinc.com) Received: by mail-pl1-f174.google.com with SMTP id o2so2163806plg.4 for ; Fri, 24 Mar 2023 08:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1679672628; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b3As057EU8x8wBZubqTCNJjhtzt8OPMGcg7Ttdeh8KU=; b=l9JmMNDQniaQPhNwsuE7R1FI0akRrjfR4dIeF/I+YhxbNb6D3AXjHR/p/Y/vZZe1KZ lqAHArB9ZMduXiL3QzQwZzziKLYQGNNtnHtNafXbaKk9sxlU6zU0zk5Zj8T2FQXg/M7K rriRC7tZB/8foAgTRjHHSsMgou0Qlqz9ZOKAFNE2DzZvnFNXI4Ceiky8l5/1Swu1vbHd gvMCiXjbIidB1fsJ85GCYrUs/h5RGe8s69/9GOpYBx24oOEyG4GR61T5gqmGZorW8QFK g5iJ1AJihErX8+oIWy4XgtIri7Ncf/Ghy3whfRRB9i9dT4bwLsKrU2I1/ROyP3pOf6Ns sU8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679672628; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b3As057EU8x8wBZubqTCNJjhtzt8OPMGcg7Ttdeh8KU=; b=ySEPKiOXQY5mcrCIRMsurCt1ENVl4btJzUfFqDdMAeYY6DuE0F1Z76uP4jc49ywLrK ZWZGHG8kCXcd2dW+zXl2UW6a7kNZkhYpfdinAcAvRc7848eTg2SDTzGmx0qbY2SGWIXf 9OGMmd435aORLsC79/Lf5mwh/+Jp/zFKkZFQpxooZX4F0dgmOeTr7/h3Pm9mcH0Kmmpq buVJeVymuP5kgI7Xe2+dLk5ByynB9YkFXr520c8XKzH2xG82UPXLHclwaqvtHKOc0NUu N5RAB1fTXUllWtnE7fzypzpG5aab0a3xozPZMyNbShzB8LendTzQYw721ZSlqJ8PympS Og2g== X-Gm-Message-State: AAQBX9dmmAo2ib9jvGyOYwwLGE9WPHdzW2p/C5EFZqvlPS0XYMFyzS5Y 1SdPv2Z9i1Lzpjl9r5Hrw004/56V83OI+FiBcog= X-Google-Smtp-Source: AKy350ayoIMTGDKKXt9QnnL2qqomyYLsGn7cYdPk6VO6Sr0uOZr/6roJbTflj1i7VzUCplsbYoLr3w== X-Received: by 2002:a17:903:27ce:b0:19c:da7f:a234 with SMTP id km14-20020a17090327ce00b0019cda7fa234mr2602068plb.67.1679672628564; Fri, 24 Mar 2023 08:43:48 -0700 (PDT) Return-Path: Received: from dhaval.ba.rivosinc.com ([171.76.83.64]) by smtp.gmail.com with ESMTPSA id je19-20020a170903265300b0019f3e339fb4sm14365369plb.187.2023.03.24.08.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 08:43:48 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Sunil V L , Andrei Warkentin , Daniel Schaefer Subject: [PATCH v1 1/2] MdePkg/BaseCacheMaintenanceLib: Enable RISCV CMO Date: Fri, 24 Mar 2023 21:13:41 +0530 Message-Id: <20230324154342.180062-2-dhaval@rivosinc.com> X-Mailer: git-send-email 2.40.0.rc0.57.g454dfcbddf In-Reply-To: <20230324154342.180062-1-dhaval@rivosinc.com> References: <20230324154342.180062-1-dhaval@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Adding code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: 1. CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available 2. Current implementation uses ifence instructions but it maybe platform specific. Many platforms may not support cache Operations based on ifence. 3. For now adding CMO on top of ifence as it is not considered harmful. 4. This requires support for GCC12.2 onwards. Test: 1. Ensured correct instructions are refelecting in asm 2. Able to boot platform with RiscVVirtQemu config 3. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Sunil V L Cc: Andrei Warkentin Cc: Daniel Schaefer Signed-off-by: Dhaval Sharma --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 126 ++++++++++++++++= ++-- MdePkg/Library/BaseLib/RiscV64/RiscVCpuCache.S | 23 ++++ 3 files changed, 143 insertions(+), 7 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3a48492b1a01..0d6d6b7414c8 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -398,6 +398,7 @@ [Sources.RISCV64] RiscV64/MemoryFence.S | GCC=0D RiscV64/RiscVSetJumpLongJump.S | GCC=0D RiscV64/RiscVCpuBreakpoint.S | GCC=0D + RiscV64/RiscVCpuCache.S | GCC=0D RiscV64/RiscVCpuPause.S | GCC=0D RiscV64/RiscVInterrupt.S | GCC=0D RiscV64/FlushCache.S | GCC=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..8e88b8391a74 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -10,9 +10,111 @@ #include =0D #include =0D =0D +/**=0D + Use runtime discovery mechanism in future when avalable=0D + through https://lists.riscv.org/g/tech-privileged/topic/83853282=0D +**/=0D +#define RV64_CACHE_BLOCK_SIZE 64=0D +=0D +typedef enum{=0D + cln,=0D + flsh,=0D + invd,=0D +}CACHE_OP;=0D +=0D +/* Ideally we should do this through BaseLib.h by adding=0D + Asm*CacheLine functions. This can be done after Initial=0D + RV refactoring is complete. For now call functions directly=0D +*/=0D +VOID=0D +EFIAPI RiscVCpuCacheFlush (=0D + UINTN=0D + );=0D +=0D +VOID=0D +EFIAPI RiscVCpuCacheClean (=0D + UINTN=0D + );=0D +=0D +VOID=0D +EFIAPI RiscVCpuCacheInval (=0D + UINTN=0D + );=0D +=0D +/**=0D + Performs required opeartion on cache lines in the cache coherency domain= =0D + of the calling CPU. If Address is not aligned on a cache line boundary,= =0D + then entire cache line containing Address is operated. If Address + Leng= th=0D + is not aligned on a cache line boundary, then the entire cache line=0D + containing Address + Length -1 is operated.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param Address The base address of the cache lines to=0D + invalidate. If the CPU is in a physical addressing mode,= then=0D + Address is a physical address. If the CPU is in a virtua= l=0D + addressing mode, then Address is a virtual address.=0D +=0D + @param Length The number of bytes to invalidate from the instruction c= ache.=0D +=0D + @return Address.=0D +=0D +**/=0D +=0D +VOID *=0D +EFIAPI=0D +CacheOpCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length,=0D + IN CACHE_OP op=0D + )=0D +{=0D + UINTN CacheLineSize;=0D + UINTN Start;=0D + UINTN End;=0D +=0D + if (Length =3D=3D 0) {=0D + return Address;=0D + }=0D +=0D + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address));=0D +=0D + //=0D + // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H=0D + //=0D + CacheLineSize =3D RV64_CACHE_BLOCK_SIZE;=0D +=0D + Start =3D (UINTN)Address;=0D + //=0D + // Calculate the cache line alignment=0D + //=0D + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1)= ;=0D + Start &=3D ~((UINTN)CacheLineSize - 1);=0D +=0D + do {=0D + switch (op) {=0D + case invd:=0D + RiscVCpuCacheInval(Start);=0D + break;=0D + case flsh:=0D + RiscVCpuCacheFlush(Start);=0D + break;=0D + case cln:=0D + RiscVCpuCacheClean(Start);=0D + break;=0D + default:=0D + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported operation\n"));=0D + break;=0D + }=0D +=0D + Start =3D Start + CacheLineSize;=0D + } while (Start !=3D End);=0D +=0D + return Address;=0D +}=0D +=0D /**=0D RISC-V invalidate instruction cache.=0D -=0D **/=0D VOID=0D EFIAPI=0D @@ -22,7 +124,6 @@ RiscVInvalidateInstCacheAsm ( =0D /**=0D RISC-V invalidate data cache.=0D -=0D **/=0D VOID=0D EFIAPI=0D @@ -32,7 +133,9 @@ RiscVInvalidateDataCacheAsm ( =0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D - calling CPU.=0D + calling CPU. This may not clear $IC on all RV implementations.=0D + RV CMO only offers block operations as per spec. Entire cache invd will = be=0D + platform dependent implementation.=0D =0D **/=0D VOID=0D @@ -77,11 +180,13 @@ InvalidateInstructionCacheRange ( )=0D {=0D DEBUG (=0D - (DEBUG_WARN,=0D + (DEBUG_ERROR,=0D "%a:RISC-V unsupported function.\n"=0D "Invalidating the whole instruction cache instead.\n", __func__)=0D );=0D InvalidateInstructionCache ();=0D + //RV does not support $I specific operation.=0D + CacheOpCacheRange(Address, Length, invd);=0D return Address;=0D }=0D =0D @@ -93,6 +198,8 @@ InvalidateInstructionCacheRange ( of the calling CPU. This function guarantees that all dirty cache lines = are=0D written back to system memory, and also invalidates all the data cache l= ines=0D in the cache coherency domain of the calling CPU.=0D + RV CMO only offers block operations as per spec. Entire cache invd will = be=0D + platform dependent implementation.=0D =0D **/=0D VOID=0D @@ -137,7 +244,7 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + CacheOpCacheRange(Address, Length, flsh);=0D return Address;=0D }=0D =0D @@ -149,6 +256,8 @@ WriteBackInvalidateDataCacheRange ( CPU. This function guarantees that all dirty cache lines are written bac= k to=0D system memory. This function may also invalidate all the data cache line= s in=0D the cache coherency domain of the calling CPU.=0D + RV CMO only offers block operations as per spec. Entire cache invd will = be=0D + platform dependent implementation.=0D =0D **/=0D VOID=0D @@ -192,7 +301,7 @@ WriteBackDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + CacheOpCacheRange(Address, Length, cln);=0D return Address;=0D }=0D =0D @@ -205,6 +314,8 @@ WriteBackDataCacheRange ( written back to system memory. It is typically used for cache diagnostic= s. If=0D the CPU does not support invalidation of the entire data cache, then a w= rite=0D back and invalidate operation should be performed on the entire data cac= he.=0D + RV CMO only offers block operations as per spec. Entire cache invd will = be=0D + platform dependent implementation.=0D =0D **/=0D VOID=0D @@ -250,6 +361,7 @@ InvalidateDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + //RV does not support $D specific operation.=0D + CacheOpCacheRange(Address, Length, invd);=0D return Address;=0D }=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuCache.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuCache.S new file mode 100644 index 000000000000..0913ed3e9221 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuCache.S @@ -0,0 +1,23 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// CpuPause for RISC-V=0D +//=0D +// Copyright (c) 2022, Rivos Inc. All rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +ASM_GLOBAL ASM_PFX(RiscVCpuCacheFlush)=0D +ASM_PFX(RiscVCpuCacheFlush):=0D + cbo.flush (a0)=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX(RiscVCpuCacheClean)=0D +ASM_PFX(RiscVCpuCacheClean):=0D + cbo.clean (a0)=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX(RiscVCpuCacheInval)=0D +ASM_PFX(RiscVCpuCacheInval):=0D + cbo.inval (a0)=0D + ret=0D --=20 2.40.0.rc0.57.g454dfcbddf