From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.31896.1679914919595753197 for ; Mon, 27 Mar 2023 04:01:59 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Q15PW1q3; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2ACCE61043; Mon, 27 Mar 2023 11:01:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 145A0C433A0; Mon, 27 Mar 2023 11:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679914918; bh=x+mH2NK6+tYTT165HVdjL2sf+Vrr4+DpJrVRNeu1f7Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q15PW1q3LG/KzOGisu8Cj3b0PaHfrykuHgjNEM+s30+AdlxV4r4hLcaDolCptH2AR Onkpd+0gpXWT3Yg7duW7QSZKrX+Kw/+VoTwfw1TOFzQ8yKbLS3XIBu2nKrHIUhXOPs E4qbDvv3UlvE9mKXsET4s9IHL1tke5FvORnZX59VwaOknh8V8PgUX4ADH3Q2Iqeqq5 X2S1hbZAeMoRBaPzqdTm/VDBWKtNw2OCtAifR1pir24H0Tf4maG1a/vGnP/kB+H3ZR aa8p64db1zZxcw6fz5hHHN+AUwU93nCCBETyqRs0dWn8Ov8aCsvdR0vcScEZy4Q8pN RzgcmQ3pRtc7A== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe , =?UTF-8?q?Marvin=20H=C3=A4user?= , Bob Feng Subject: [PATCH v2 09/17] ArmPkg: Emit BTI opcodes when BTI codegen is enabled Date: Mon, 27 Mar 2023 13:01:04 +0200 Message-Id: <20230327110112.262503-10-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327110112.262503-1-ardb@kernel.org> References: <20230327110112.262503-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable When building with -mbranch-protection=3Dbti, which affects the compiler codegen only, ensure that the assembler based codegen is aligned with this, by emitting the BTI C opcode at the start of each exported function. While most exported functions are not in fact ever called indirectly, whether or not this is the case is a property of the caller so annotating every exported function is a reasonable default. While at it, fix two occurrences in ArmPkg of exported functions that did not use the ASM_FUNC() macro. Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/AsmMacroIoLibV8.h | 3 ++- ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 3 +-- ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S | 4 +--- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacroIoLi= bV8.h index 2c2b1cabd0537671..135aaeca5d0b986d 100644 --- a/ArmPkg/Include/AsmMacroIoLibV8.h +++ b/ArmPkg/Include/AsmMacroIoLibV8.h @@ -38,7 +38,8 @@ .global Name ; \=0D .section #Section, "ax" ; \=0D .type Name, %function ; \=0D - Name:=0D + Name: ; \=0D + AARCH64_BTI(c)=0D =0D #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D =0D diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/Ar= mPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index 9202952ee9c0d4e5..cd9437b6aab82889 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -94,7 +94,6 @@ =0D GCC_ASM_EXPORT(ExceptionHandlersEnd)=0D GCC_ASM_EXPORT(CommonCExceptionHandler)=0D -GCC_ASM_EXPORT(RegisterEl0Stack)=0D =0D .text=0D =0D @@ -387,6 +386,6 @@ ASM_PFX(CommonExceptionEntry): =0D eret=0D =0D -ASM_PFX(RegisterEl0Stack):=0D +ASM_FUNC(RegisterEl0Stack)=0D msr sp_el0, x0=0D ret=0D diff --git a/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S b/ArmPkg/Library/Arm= SvcLib/AArch64/ArmSvc.S index 1a7c10cb793183e7..ab13914fd3e7a359 100644 --- a/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S +++ b/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S @@ -8,9 +8,7 @@ .text=0D .align 3=0D =0D -GCC_ASM_EXPORT(ArmCallSvc)=0D -=0D -ASM_PFX(ArmCallSvc):=0D +ASM_FUNC(ArmCallSvc)=0D // Push frame pointer and return address on the stack=0D stp x29, x30, [sp, #-32]!=0D mov x29, sp=0D --=20 2.39.2