From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.32012.1679914902986054583 for ; Mon, 27 Mar 2023 04:01:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=H0U8pfXu; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 678E2611AF; Mon, 27 Mar 2023 11:01:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BE8AC433EF; Mon, 27 Mar 2023 11:01:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679914900; bh=N1GR8MJl/fjMlFZg6dHm7KE8/tHZl4884v8kTftEsC0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H0U8pfXuTWngO2XhiAEgOOeA3C/Jn3CTYphszpEBlZDvF7f//x6Kl7l+i0TcvVmt8 ZVLlBYj1E7FjGBN11sGoeDFiLzrKSedVWiekGsaOhZaRLMat1j8LnCRG87kiXGJam2 fVUI0HorIIPOXkwo0jQ57E+Pr94FKIXAAjXJZmR7iYuy5lBTR6lpkjPZYjSZpr4Oeq RMvl+2mXNUBzn7x7NXdMRkWmskSxsz1v8rBsAfGCVsxiFeiZdJ9fh2OkbaCKbbQAtD LMasCgqyhcdBnOAqbxDLB91bJmvQCHAO1ofkNTfsjfhZQiJMvZCVUotMCKwmvQXjlT 8ChzljXoZIq4w== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe , =?UTF-8?q?Marvin=20H=C3=A4user?= , Bob Feng Subject: [PATCH v2 03/17] MdePkg/BaseIoLibIntrinsic AARCH64: Make asm files BTI compatible Date: Mon, 27 Mar 2023 13:00:58 +0200 Message-Id: <20230327110112.262503-4-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327110112.262503-1-ardb@kernel.org> References: <20230327110112.262503-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S | 2 ++ MdePkg/Library/BaseIoLibIntrinsic/AArch64/ArmVirtMmio.S | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S b/ArmVirtPkg/Lib= rary/ArmPlatformLibQemu/IdMap.S index 584ffcb3ebe2ef34..b67f09ab61f2474e 100644 --- a/ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S @@ -57,3 +57,5 @@ idmap: /* level 0 */ .quad PAGE_XIP | (idx << 12) // 2044 KiB of R-X flash mapping= s=0D .set idx, idx + 1=0D .endr=0D +=0D +AARCH64_BTI()=0D diff --git a/MdePkg/Library/BaseIoLibIntrinsic/AArch64/ArmVirtMmio.S b/MdeP= kg/Library/BaseIoLibIntrinsic/AArch64/ArmVirtMmio.S index 00f1abec15f0ef08..77f562697ef971b5 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/AArch64/ArmVirtMmio.S +++ b/MdePkg/Library/BaseIoLibIntrinsic/AArch64/ArmVirtMmio.S @@ -29,6 +29,7 @@ GCC_ASM_EXPORT(MmioWrite64Internal) // @return The value read.=0D //=0D ASM_PFX(MmioRead8Internal):=0D + AARCH64_BTI(c)=0D ldrb w0, [x0]=0D dmb ld=0D ret=0D @@ -44,6 +45,7 @@ ASM_PFX(MmioRead8Internal): // @param Value The value to write to the MMIO register.=0D //=0D ASM_PFX(MmioWrite8Internal):=0D + AARCH64_BTI(c)=0D dmb st=0D strb w1, [x0]=0D ret=0D @@ -60,6 +62,7 @@ ASM_PFX(MmioWrite8Internal): // @return The value read.=0D //=0D ASM_PFX(MmioRead16Internal):=0D + AARCH64_BTI(c)=0D ldrh w0, [x0]=0D dmb ld=0D ret=0D @@ -75,6 +78,7 @@ ASM_PFX(MmioRead16Internal): // @param Value The value to write to the MMIO register.=0D //=0D ASM_PFX(MmioWrite16Internal):=0D + AARCH64_BTI(c)=0D dmb st=0D strh w1, [x0]=0D ret=0D @@ -91,6 +95,7 @@ ASM_PFX(MmioWrite16Internal): // @return The value read.=0D //=0D ASM_PFX(MmioRead32Internal):=0D + AARCH64_BTI(c)=0D ldr w0, [x0]=0D dmb ld=0D ret=0D @@ -106,6 +111,7 @@ ASM_PFX(MmioRead32Internal): // @param Value The value to write to the MMIO register.=0D //=0D ASM_PFX(MmioWrite32Internal):=0D + AARCH64_BTI(c)=0D dmb st=0D str w1, [x0]=0D ret=0D @@ -122,6 +128,7 @@ ASM_PFX(MmioWrite32Internal): // @return The value read.=0D //=0D ASM_PFX(MmioRead64Internal):=0D + AARCH64_BTI(c)=0D ldr x0, [x0]=0D dmb ld=0D ret=0D @@ -137,6 +144,7 @@ ASM_PFX(MmioRead64Internal): // @param Value The value to write to the MMIO register.=0D //=0D ASM_PFX(MmioWrite64Internal):=0D + AARCH64_BTI(c)=0D dmb st=0D str x1, [x0]=0D ret=0D --=20 2.39.2