From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.25857.1680184299638257626 for ; Thu, 30 Mar 2023 06:51:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=WNQpaTAc; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 92FA5B828F3; Thu, 30 Mar 2023 13:51:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70DF3C4339E; Thu, 30 Mar 2023 13:51:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680184296; bh=9iI1D5CbyV2o/2hFKV1Sl1MxZ4GZi5Lqp9NhBbH9ShA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WNQpaTAcqNndalPLGw9ryW3iIt5VcaQ6/eK2Q/VUZgi+vEUl2uVZNG4ibMYnI7fsz Fe/UnNJy+opBCIm1gyP4fz8oI2Z+gds+QDfrRkxNM2L2SAmYbkVB4cigDsRzI8qWYo wy0NMI9TiTl9rO5W03GEXA16Sv2uS8f7d0W8xJSXmuJdoAfKbcFte3RZggMwImjEme yeIy4k51jeB5uLqW9K42gwenn4sOfpsbw+pa5NIrSBs/VAENSo1HQ27QuNQ1U/Yrt6 d4XsKGyP+ZTmfpHQ1X0b0dzMu0m15ASEDFRIp7bnvhuHQmDQtLkPeYPAISlbO8CBAa 0sDwiK9dUWyxw== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ni, Ray , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky Subject: [PATCH 1/4] UefiCpuPkg/CpuExceptionHandlerLib: Create LLD compatible SEC/PEI version Date: Thu, 30 Mar 2023 15:51:19 +0200 Message-Id: <20230330135122.1445353-2-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330135122.1445353-1-ardb@kernel.org> References: <20230330135122.1445353-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Currently, we use the non-Xcode5 version of ExceptionHandlerAsm.nasm only for the SEC and PEI phases, and this version is not compatible with the LLD linker, which does not permit absolute relocations in read-only sections. Let's rename the .nasm file to reflect this, and tweak it so that LLD accepts it as well. This involves using relative references where possible, and moving the template code (which is never executed directly) into the .data section. Since this makes the generic version compatible with the XCODE5 version, let's use this [smaller] version for XCODE5 builds too. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf= | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{ExceptionHandlerAsm.nasm = =3D> SecPeiExceptionHandlerAsm.nasm} | 11 ++++++----- UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerL= ib.inf | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index df44371fe018e06d..10c5c5f2e5d203f6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHan= dlerAsm.nasm similarity index 95% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerA= sm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHand= lerAsm.nasm index aaf8d622e6f3b8f1..84d51bf6302e1dcb 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHandlerA= sm.nasm @@ -27,7 +27,6 @@ extern ASM_PFX(CommonExceptionHandler) SECTION .data=0D =0D DEFAULT REL=0D -SECTION .text=0D =0D ALIGN 8=0D =0D @@ -51,6 +50,9 @@ HookAfterStubHeaderBegin: push rax=0D mov rax, HookAfterStubHeaderEnd=0D jmp rax=0D +=0D +SECTION .text=0D +=0D HookAfterStubHeaderEnd:=0D mov rax, rsp=0D and sp, 0xfff0 ; make sure 16-byte aligned for exception c= ontext=0D @@ -276,8 +278,7 @@ DrFinish: ; and make sure RSP is 16-byte aligned=0D ;=0D sub rsp, 4 * 8 + 8=0D - mov rax, ASM_PFX(CommonExceptionHandler)=0D - call rax=0D + call ASM_PFX(CommonExceptionHandler)=0D add rsp, 4 * 8 + 8=0D =0D cli=0D @@ -384,10 +385,10 @@ DoIret: ; comments here for definition of address map=0D global ASM_PFX(AsmGetTemplateAddressMap)=0D ASM_PFX(AsmGetTemplateAddressMap):=0D - mov rax, AsmIdtVectorBegin=0D + lea rax, [AsmIdtVectorBegin]=0D mov qword [rcx], rax=0D mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32= =0D - mov rax, HookAfterStubHeaderBegin=0D + lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D ret=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 619b39d7f1de9ae3..c58fbb0d74500e48 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -33,7 +33,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D --=20 2.39.2