From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web10.25631.1680184301699630357 for ; Thu, 30 Mar 2023 06:51:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=afLNszvd; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CA035B828F2; Thu, 30 Mar 2023 13:51:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE0C2C433A1; Thu, 30 Mar 2023 13:51:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680184298; bh=jT48L7tUskr9hMzQOgB2BtflPe1zDNU+/qCDZaqGaSA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=afLNszvdQkEmK1d3W9XgO01G3M4nExxu1yQr/vrJywfNgmnMlfiTp15OFgXqxjEeR vBSEL1bdruwpUMqiXSMfgA1OnwO8YPX2Z7bAXCKuvpRvDyWYppp+qCljvnWFk6UmRg PF04J1krVSz9S5oqjCXf2B9Lq7tRYe6ns4EVk8ouaJ6sz+3DYjyDff0o7CiFrLukul OIwCXO/Egk+vR+NT4TzNrIZ8JDbIKIlqwvuGSrpli46U+PS7miy/lwXrV/sTOUwVEd 90t1A0Y9e8RW8cx6ruZ+oZGnTsMAWC6MkhAsj2mw4gSmkqpnTI5Ws3ISGKnn1zIFkG 4FDkpAa7irW4A== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ni, Ray , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky Subject: [PATCH 2/4] UefiCpuPkg/CpuExceptionHandlerLib: Remove pointless runtime fixups Date: Thu, 30 Mar 2023 15:51:20 +0200 Message-Id: <20230330135122.1445353-3-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330135122.1445353-1-ardb@kernel.org> References: <20230330135122.1445353-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The XCODE5 compatible version of ExceptionHandlerAsm, which is in fact used for all builds of this library except the SecPei flavor, performs runtime fixups that are not really necessary: we can just move the code templates into the .data section where absolute relocations are permitted. So simplify the code, and rename it to ExceptionHandlerAsm.nasm to reflect the reality that this code is not Xcode5 specific. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf = | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf = | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{Xcode5ExceptionHandlerAsm.n= asm =3D> ExceptionHandlerAsm.nasm} | 22 +++++--------------- 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index d0f82095cf926e99..1b2dde746d154706 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index 5339f8e604045801..86248cea3e97cedb 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 8f8a5dab79303f87..0eed594be8660302 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHan= dlerAsm.nasm similarity index 92% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHa= ndlerAsm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm= .nasm index 957478574253e619..55a58c6a58858c81 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -49,7 +49,6 @@ extern ASM_PFX(CommonExceptionHandler) SECTION .data=0D =0D DEFAULT REL=0D -SECTION .text=0D =0D ALIGN 8=0D =0D @@ -59,7 +58,7 @@ AsmIdtVectorBegin: %rep 256=0D push strict dword %[Vector] ; This instruction pushes sign-extended= 8-byte value on stack=0D push rax=0D - mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptE= ntry)=0D + mov rax, ASM_PFX(CommonInterruptEntry)=0D jmp rax=0D %assign Vector Vector+1=0D %endrep=0D @@ -69,9 +68,11 @@ HookAfterStubHeaderBegin: push strict dword 0 ; 0 will be fixed=0D VectorNum:=0D push rax=0D - mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd= =0D -JmpAbsoluteAddress:=0D + mov rax, HookAfterStubHeaderEnd=0D jmp rax=0D +=0D +SECTION .text=0D +=0D HookAfterStubHeaderEnd:=0D mov rax, rsp=0D and sp, 0xfff0 ; make sure 16-byte aligned for exception c= ontext=0D @@ -456,19 +457,6 @@ ASM_PFX(AsmGetTemplateAddressMap): mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 25= 6=0D lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D -=0D -; Fix up CommonInterruptEntry address=0D - lea rax, [ASM_PFX(CommonInterruptEntry)]=0D - lea rcx, [AsmIdtVectorBegin]=0D -%rep 256=0D - mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBegin= )], rax=0D - add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 256=0D -%endrep=0D -; Fix up HookAfterStubHeaderEnd=0D - lea rax, [HookAfterStubHeaderEnd]=0D - lea rcx, [JmpAbsoluteAddress]=0D - mov qword [rcx - 8], rax=0D -=0D ret=0D =0D ;-------------------------------------------------------------------------= ------------=0D --=20 2.39.2