From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web10.39115.1680211284286122875 for ; Thu, 30 Mar 2023 14:21:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=V8QXF3D8; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8816FB82A38; Thu, 30 Mar 2023 21:21:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87082C433D2; Thu, 30 Mar 2023 21:21:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680211281; bh=zf9zcfDBUtZQ+RC+haE/aRv85gIhRpSeB0Q0oiAAPyY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V8QXF3D89x06qX0U2Kr7GwZn1vY6MgKYoTfl5UqwtdzpVb4xtj1wl3yrAnn7BsnDq xNwE+W/6G2Bi7X9bWtEFAZRfxHTVL5rw3wkvfTR6B/jtoQWuFBguMcpdQwHMgffA37 EkYBnXx5ET6o53iEIO0piM+aS+2lpeqDRh/8VtpukAsVmEGXTN3nhnKsHnh3uoeX+e XDKGXSN5/iFIS9d6QUb8moSK7S/qDmbeR7e4S5KyW6UW2h26HhNSd4W93Qd33rexiJ qBfsberOB/7WDxCgL2sLJ4clxaWS/eWGlFCHMQVQ35CQFrdjaPhMXW3p6oy4+4K5Uo ZfvN/izdyfmXQ== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ni, Ray , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky Subject: [RFT PATCH v2 3/6] UefiCpuPkg/CpuExceptionHandlerLib: Use single SEC/PEI version Date: Thu, 30 Mar 2023 23:20:58 +0200 Message-Id: <20230330212101.1566931-4-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330212101.1566931-1-ardb@kernel.org> References: <20230330212101.1566931-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Currently, we use the non-Xcode5 version of ExceptionHandlerAsm.nasm only for the SEC and PEI phases, and this version was not compatible with the XCODE or LLD linkers, which do not permit absolute relocations in read-only sections by default. This has been fixed now, so we can use it for all toolchains. Let's rename the .nasm file to reflect the fact that is used for the SecPei flavor of this library only, and while at it, remove some unnecessary absolute references. Since this makes the generic version compatible with the XCODE, let's use this [smaller] version for XCODE5 builds too. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf= | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{ExceptionHandlerAsm.nasm = =3D> SecPeiExceptionHandlerAsm.nasm} | 7 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerL= ib.inf | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index df44371fe018e06d..10c5c5f2e5d203f6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHan= dlerAsm.nasm similarity index 95% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerA= sm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHand= lerAsm.nasm index aaf8d622e6f3b8f1..585298768a66af6a 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHandlerA= sm.nasm @@ -276,8 +276,7 @@ DrFinish: ; and make sure RSP is 16-byte aligned=0D ;=0D sub rsp, 4 * 8 + 8=0D - mov rax, ASM_PFX(CommonExceptionHandler)=0D - call rax=0D + call ASM_PFX(CommonExceptionHandler)=0D add rsp, 4 * 8 + 8=0D =0D cli=0D @@ -384,10 +383,10 @@ DoIret: ; comments here for definition of address map=0D global ASM_PFX(AsmGetTemplateAddressMap)=0D ASM_PFX(AsmGetTemplateAddressMap):=0D - mov rax, AsmIdtVectorBegin=0D + lea rax, [AsmIdtVectorBegin]=0D mov qword [rcx], rax=0D mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32= =0D - mov rax, HookAfterStubHeaderBegin=0D + lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D ret=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 619b39d7f1de9ae3..c58fbb0d74500e48 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -33,7 +33,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D --=20 2.39.2