From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.50284.1680254096292660682 for ; Fri, 31 Mar 2023 02:14:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=oh3HJYO0; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A55E2B82D11; Fri, 31 Mar 2023 09:14:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A538C4339E; Fri, 31 Mar 2023 09:14:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680254093; bh=faq+eyh96fdF3CT0j8ob0fq5qDyOhNYhW5j44GohPTs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oh3HJYO0ByphE2wUqbFrTr7T0IpfiolHzx4yQjH7h32IRA2GY6NYgW1xbx5ZDcv+Q Zbj3F/SYHwGUtRgZox000x37bWQ+Wb5M26wptd69Atbx4wuW26TSVGaUgdOWRvbwzz S4X7f0aH2QZ1tLo0LsvNUCOoN7C9+AuHnciNGsagusDyYxCdzYrmZjKyTB9KCg7XE9 qmRdp9//b488QCV35s2eNdmfTpdJUm91Jjpt4uHtDRutddDaPS2AWFFGNf2BK2z/us mweeYNRT3wZWkeJ7I6dQbn6gniDsoOA+ytZbWK1b0nS2Az0o1IiX05alP5M11r4Lkz dsa2DDZSK4gmQ== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , "Ni, Ray" , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky , =?UTF-8?q?Marvin=20H=C3=A4user?= Subject: [RFT PATCH v3 2/5] UefiCpuPkg/CpuExceptionHandlerLib: Use single SEC/PEI version Date: Fri, 31 Mar 2023 11:14:34 +0200 Message-Id: <20230331091437.1593337-3-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230331091437.1593337-1-ardb@kernel.org> References: <20230331091437.1593337-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Currently, we use the non-Xcode5 version of ExceptionHandlerAsm.nasm only for the SEC and PEI phases, and this version was not compatible with the XCODE or LLD linkers, which do not permit absolute relocations in read-only sections. Given that SEC and PEI code typically executes in place from flash and does not use page alignment for sections, we can simply emit the code carrying the absolute symbol references into the .data segment instead. This works around the linker's objections, and the resulting image will be mapped executable in its entirety anyway. Since this is only needed for XCODE, let's make this change conditionally using a preprocessor macro. Let's rename the .nasm file to reflect the fact that is used for the SecPei flavor of this library only, and while at it, remove some unnecessary absolute references. Also update the Xcode specific version of this library, and use this source file instead. This is necesessary, as the Xcode specific version modifies its own code at runtime, which is not permitted in SEC or PEI. Note that this also removes CET support from the Xcode5 specific build of the SEC/PEI version of this library, but this is not needed this early in any case, and this aligns it with other toolchains, which use this version of the library, which does not have CET support either. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf= | 4 +++- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{ExceptionHandlerAsm.nasm = =3D> SecPeiExceptionHandlerAsm.nasm} | 12 ++++++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerL= ib.inf | 4 +++- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index df44371fe018e06d..885bb6638ab58620 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -58,3 +58,5 @@ [Pcd] [FeaturePcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES=0D =0D +[BuildOptions]=0D + XCODE:*_*_X64_PP_FLAGS =3D -DNO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHan= dlerAsm.nasm similarity index 94% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerA= sm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHand= lerAsm.nasm index aaf8d622e6f3b8f1..ec45c60181906c14 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/SecPeiExceptionHandlerA= sm.nasm @@ -27,7 +27,9 @@ extern ASM_PFX(CommonExceptionHandler) SECTION .data=0D =0D DEFAULT REL=0D +#ifndef NO_ABSOLUTE_RELOCS_IN_TEXT=0D SECTION .text=0D +#endif=0D =0D ALIGN 8=0D =0D @@ -51,6 +53,9 @@ HookAfterStubHeaderBegin: push rax=0D mov rax, HookAfterStubHeaderEnd=0D jmp rax=0D +=0D +SECTION .text=0D +=0D HookAfterStubHeaderEnd:=0D mov rax, rsp=0D and sp, 0xfff0 ; make sure 16-byte aligned for exception c= ontext=0D @@ -276,8 +281,7 @@ DrFinish: ; and make sure RSP is 16-byte aligned=0D ;=0D sub rsp, 4 * 8 + 8=0D - mov rax, ASM_PFX(CommonExceptionHandler)=0D - call rax=0D + call ASM_PFX(CommonExceptionHandler)=0D add rsp, 4 * 8 + 8=0D =0D cli=0D @@ -384,10 +388,10 @@ DoIret: ; comments here for definition of address map=0D global ASM_PFX(AsmGetTemplateAddressMap)=0D ASM_PFX(AsmGetTemplateAddressMap):=0D - mov rax, AsmIdtVectorBegin=0D + lea rax, [AsmIdtVectorBegin]=0D mov qword [rcx], rax=0D mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32= =0D - mov rax, HookAfterStubHeaderBegin=0D + lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D ret=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 619b39d7f1de9ae3..17f872bb15eb0ff7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -33,7 +33,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/SecPeiExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -63,3 +63,5 @@ [Pcd] [FeaturePcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES=0D =0D +[BuildOptions]=0D + XCODE:*_*_X64_PP_FLAGS =3D -DNO_ABSOLUTE_RELOCS_IN_TEXT=0D --=20 2.39.2