From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.50285.1680254096714938104 for ; Fri, 31 Mar 2023 02:14:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=EKdjXWyE; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 40437625F3; Fri, 31 Mar 2023 09:14:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1006C433A1; Fri, 31 Mar 2023 09:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680254095; bh=TyCNywsNPYqHvpaFH+U7V27GhpAXVquAxtMiF4H51RE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EKdjXWyEQry/rE+hc2tXl2/meTOE3BKOQX60EF9H3xX5tUyI/oVDVy93U5sce5nYL 4TldCDkuiyOriymGoIuFhLKyu6VbWWBE6bknSQMjYxBbmCW/3ofwYTM7TVLUVDrqn4 XlP/M2m4hHCA+cRmMWT5j5Pk08rnPXJ7eCkvyBbML1656RARFOEuGIFDenPZUNYKXK PWGfbXH5gEilt4+2SxhUb1MK5PNw5+N1C2KWBr8sTdwoFwnLd+z9UYP8fZTRY/6jte ngGsrhGv76/vprGLmFpwYMsS1tVk34alY1Pr1s/Pdnl5k707iR3Po2IhBl23A1AI/h Z/KE4V7TC5yng== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , "Ni, Ray" , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky , =?UTF-8?q?Marvin=20H=C3=A4user?= Subject: [RFT PATCH v3 3/5] UefiCpuPkg/CpuExceptionHandlerLib: Make runtime fixups XCODE-only Date: Fri, 31 Mar 2023 11:14:35 +0200 Message-Id: <20230331091437.1593337-4-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230331091437.1593337-1-ardb@kernel.org> References: <20230331091437.1593337-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The CPU exception handler library code was rewritten at some point to populate the vector code templates with absolute references at runtime, given that the XCODE linker does not permit absolute references in executable code when creating PIE executables. This is rather unfortunate, as this prevents us from using strict permissions on the memory mappings, given that the .text section needs to be writable at runtime for this arrangement to work. So let's make this hack XCODE-only, by setting a preprocessor #define from the command line when using the XCODE toolchain, and only including the runtime fixup code when the macro is defined. While at it, rename the Xcode5ExceptionHandlerAsm.nasm source file and drop the Xcode5 prefix: this code is used by other toolchains too. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 5 ++++- UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf = | 4 +++- UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf = | 4 +++- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{Xcode5ExceptionHandlerAsm.n= asm =3D> ExceptionHandlerAsm.nasm} | 10 ++++++++++ 4 files changed, 20 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index d0f82095cf926e99..ee9df805c05df4f7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -61,3 +61,6 @@ [LibraryClasses] MemoryAllocationLib=0D DebugLib=0D CcExitLib=0D +=0D +[BuildOptions]=0D + XCODE:*_*_X64_PP_FLAGS =3D -DNO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index 5339f8e604045801..83970c54712f22a2 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -62,3 +62,5 @@ [Pcd] [FeaturePcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES=0D =0D +[BuildOptions]=0D + XCODE:*_*_X64_PP_FLAGS =3D -DNO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 8f8a5dab79303f87..acd2936aef4490a5 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -61,3 +61,5 @@ [Pcd] [FeaturePcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES=0D =0D +[BuildOptions]=0D + XCODE:*_*_X64_PP_FLAGS =3D -DNO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHan= dlerAsm.nasm similarity index 95% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHa= ndlerAsm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm= .nasm index 957478574253e619..3823656ea7d4c3b8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -59,7 +59,11 @@ AsmIdtVectorBegin: %rep 256=0D push strict dword %[Vector] ; This instruction pushes sign-extended= 8-byte value on stack=0D push rax=0D +#ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptE= ntry)=0D +#else=0D + mov rax, ASM_PFX(CommonInterruptEntry)=0D +#endif=0D jmp rax=0D %assign Vector Vector+1=0D %endrep=0D @@ -69,8 +73,12 @@ HookAfterStubHeaderBegin: push strict dword 0 ; 0 will be fixed=0D VectorNum:=0D push rax=0D +#ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd= =0D JmpAbsoluteAddress:=0D +#else=0D + mov rax, HookAfterStubHeaderEnd=0D +#endif=0D jmp rax=0D HookAfterStubHeaderEnd:=0D mov rax, rsp=0D @@ -457,6 +465,7 @@ ASM_PFX(AsmGetTemplateAddressMap): lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D =0D +#ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D ; Fix up CommonInterruptEntry address=0D lea rax, [ASM_PFX(CommonInterruptEntry)]=0D lea rcx, [AsmIdtVectorBegin]=0D @@ -468,6 +477,7 @@ ASM_PFX(AsmGetTemplateAddressMap): lea rax, [HookAfterStubHeaderEnd]=0D lea rcx, [JmpAbsoluteAddress]=0D mov qword [rcx - 8], rax=0D +#endif=0D =0D ret=0D =0D --=20 2.39.2