From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.10047.1680304578752799245 for ; Fri, 31 Mar 2023 16:16:18 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=OMy7pqbn; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680304578; x=1711840578; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=GrCWcoU8HIeRRf8idE1KcJ6J41k5dpStX3AorKQMb4w=; b=OMy7pqbnM+rgbMOzWh2WArpQ3NqQXBkTHahLPsrEFsedKdatJzNSWUKv Y4Epld3o+byFF+bKuM/9mV2PS2QOWJ5/N4V/srjmiClgMfbe90vv5WAqr jcl8yg3pEu9ftOzsnwrZ6OrCsGOWz0raEiU4k1CWcpYnxAej4AOCirxG3 f1szNvqbiS8EVKSc9JphEB1zI51yIc7fLn8BrauN45DRirEQxaMcoDLmr 8b+jTJhQQdxLJSs9iCJk7a6ZyiKVIFNsXS9B6tkVOnh7MEvGJbovZCIQ7 2WETcPprm6374ETVN6urg1yk4b9ajrPlngGpYevK8FE/ghKaP2XTd328t A==; X-IronPort-AV: E=McAfee;i="6600,9927,10666"; a="427853782" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="427853782" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 16:16:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10666"; a="931349408" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="931349408" Received: from cchiu4-mobl.gar.corp.intel.com ([10.252.130.169]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 16:16:18 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [PATCH] IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register. Date: Fri, 31 Mar 2023 16:16:08 -0700 Message-Id: <20230331231608.1516-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 +++++++ IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 21 +++++++++++++++++= +++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index a222f2e376..016f943b43 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -157,6 +157,9 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + ; Save EBX to MM2=0D + ;=0D + movd mm2, ebx=0D mov eax, 1=0D cpuid=0D bt edx, 25=0D @@ -169,6 +172,10 @@ NextAddress: bt ecx, 19=0D jnc SseError=0D %endif=0D + ;=0D + ; Restore EBX from MM2=0D + ;=0D + movd ebx, mm2=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 38c807a311..002a5a1412 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -255,6 +255,10 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + ; Save RBX to R11=0D + ; Save RCX to R10=0D + ;=0D + mov r11, rbx=0D mov r10, rcx=0D mov rax, 1=0D cpuid=0D @@ -266,7 +270,12 @@ NextAddress: ;=0D bt ecx, 19=0D jnc SseError=0D - mov rcx, r10=0D + ;=0D + ; Restore RBX from R11=0D + ; Restore RCX from R10=0D + ;=0D + mov rbx, r11=0D + mov rcx, r10=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D @@ -284,6 +293,11 @@ NextAddress: %endmacro=0D =0D %macro ENABLE_AVX 0=0D + ;=0D + ; Save RBX to R11=0D + ; Save RCX to R10=0D + ;=0D + mov r11, rbx=0D mov r10, rcx=0D mov eax, 1=0D cpuid=0D @@ -307,6 +321,11 @@ EnableAvx: xgetbv ; result in edx:eax=0D or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state=0D xsetbv=0D + ;=0D + ; Restore RBX from R11=0D + ; Restore RCX from R10=0D + ;=0D + mov rbx, r11=0D mov rcx, r10=0D %endmacro=0D =0D --=20 2.35.0.windows.1