From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.46847.1680448715581016067 for ; Sun, 02 Apr 2023 08:18:39 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ZC+B4BAf; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680448719; x=1711984719; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5zpOO1/yP7YyjF9ZG7Zg+bUb6PeQ1YZNAow+FV3DI4g=; b=ZC+B4BAfTsQyTvqxUOAP2haKV/d93rm19B5FPrs6z5a9YkW5JPTbPS6S gQGKyHaza1BbzsHM8EKBZsV0bpdMI1Pv5oDfbxKw9vl7hG1q/dTFpeB5x l5/qL9RgUrpN2J60ydMUNq9IXkMSpS04Xnm5dQBd2+OHmki5JrkWNZW9A n12JtockcGZv/B6Ts7eaJLeCYgZKC5bNXdJGi25jQKCnl9TS4oBTRQ9ed Qgt7+PxkiR0zeRpWiwDyxwrWYZwrJQ+4OlCLrIHsqoDXrbl0C86V+/m1Q 6kOHqjPZJPCcqFSEhSKTvG6Bpg521F38TEQ+GHnCtTYzgNfm3Aie3ON4s A==; X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="321400359" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="321400359" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2023 08:18:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="679188170" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="679188170" Received: from evancy.sh.intel.com ([10.239.158.113]) by orsmga007.jf.intel.com with ESMTP; 02 Apr 2023 08:18:37 -0700 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Sunil V L , Andrei Warkentin Subject: [PATCH 4/5] Silicon/RISC-V: remove redundant function code from RiscVCpuLib Date: Sun, 2 Apr 2023 23:15:41 +0800 Message-Id: <20230402151542.325929-5-evan.chai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230402151542.325929-1-evan.chai@intel.com> References: <20230402151542.325929-1-evan.chai@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable They had been implemented in MdePkg/Library/BaseLib Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai --- Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 20 +----------= --------- Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 41 +----------= ------------------------------ 2 files changed, 2 insertions(+), 59 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index efe85489..f1555843 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -2,6 +2,7 @@ RISC-V CPU library definitions.=0D =0D Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -96,23 +97,4 @@ RiscVReadMachineImplementId ( VOID=0D );=0D =0D -VOID=0D - RiscVSetSupervisorAddressTranslationRegister (UINT64);=0D -=0D -VOID=0D - RiscVSetSupervisorScratch (UINT64);=0D -=0D -UINT64=0D -RiscVGetSupervisorScratch (=0D - VOID=0D - );=0D -=0D -VOID=0D - RiscVSetSupervisorStvec (UINT64);=0D -=0D -UINT64=0D -RiscVGetSupervisorStvec (=0D - VOID=0D - );=0D -=0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index e242c9b8..52ef0788 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -3,6 +3,7 @@ // RISC-V CPU functions.=0D //=0D // Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +// Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -101,43 +102,3 @@ ASM_FUNC (RiscVReadMachineImplementId) csrr a0, RISCV_CSR_MACHINE_MIMPID=0D ret=0D =0D -//=0D -// Set Supervisor mode scratch.=0D -// @param a0 : Value set to Supervisor mode scratch=0D -//=0D -ASM_FUNC (RiscVSetSupervisorScratch)=0D - csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0=0D - ret=0D -=0D -//=0D -// Get Supervisor mode scratch.=0D -// @retval a0 : Value in Supervisor mode scratch=0D -//=0D -ASM_FUNC (RiscVGetSupervisorScratch)=0D - csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH=0D - ret=0D -=0D -//=0D -// Set Supervisor mode trap vector.=0D -// @param a0 : Value set to Supervisor mode trap vector=0D -//=0D -ASM_FUNC (RiscVSetSupervisorStvec)=0D - csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0=0D - ret=0D -=0D -//=0D -// Get Supervisor mode scratch.=0D -// @retval a0 : Value in Supervisor mode trap vector=0D -//=0D -ASM_FUNC (RiscVGetSupervisorStvec)=0D - csrr a0, RISCV_CSR_SUPERVISOR_STVEC=0D - ret=0D -=0D -//=0D -// Set Supervisor Address Translation and=0D -// Protection Register.=0D -//=0D -ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)=0D - csrw RISCV_CSR_SUPERVISOR_SATP, a0=0D - ret=0D -=0D --=20 2.34.1