From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.46847.1680448715581016067 for ; Sun, 02 Apr 2023 08:18:43 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=iLjTr3wU; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: evan.chai@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680448723; x=1711984723; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TAmVj5ma/H6MrvEtxMV4AJfLyeuPCqVhDY5WSAa5c84=; b=iLjTr3wUxVkt6gBwt9fWECmD8aYhnrMjTcqdmztp5N74FMsITfH392xk obfnYGL3Y6Ef6QhNw1qxHwCgBxMVeA+eIY+AtcH/0qPipP+TmHJ2ssoOF hj0LOWPgkWtwaR18mucmbGiNrU0vvvbsMuwMPLFdU7IsTRn4mPvwIPotu YznHP6ToYlDxW3S011s2iowMkSgqY7Y26ZuDs7ytd+aYNN57jkdMILq6j EHn+khBUZCVORTcCeM2KIRo3T4n/GAgQ1w86MeNicD3XSxi1Cudb1J+2h f/ife0HkOd4MRO2PBI8W9VWUFnskjcaYx2q+l1yKSrKmPKcq/5YBRYo3y Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="321400377" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="321400377" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2023 08:18:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="679188176" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="679188176" Received: from evancy.sh.intel.com ([10.239.158.113]) by orsmga007.jf.intel.com with ESMTP; 02 Apr 2023 08:18:41 -0700 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Sunil V L , Andrei Warkentin Subject: [PATCH 5/5] Platform/ Siliocn/: Fix building failure caused by wrong lib. Date: Sun, 2 Apr 2023 23:15:42 +0800 Message-Id: <20230402151542.325929-6-evan.chai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230402151542.325929-1-evan.chai@intel.com> References: <20230402151542.325929-1-evan.chai@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable RiscVSbiLib was implemented in MdePkg/Library/BaseRiscVSbiLib. Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai --- Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c = | 4 +++- Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf = | 4 +++- Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf = | 3 ++- Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc = | 4 ++-- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc = | 4 ++-- Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServ= icesRuntimeDxe.inf | 2 ++ Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf = | 3 ++- 7 files changed, 16 insertions(+), 8 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c index 524b0a63..30ec8a8b 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -2,13 +2,15 @@ Reset System Library functions for RISC-V=0D =0D Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D #include =0D #include =0D -#include =0D +#include =0D =0D /**=0D This function causes a system-wide reset (cold reset), in which=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib= .inf index 8987adb9..605d9efd 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -2,6 +2,8 @@ # Library instance for ResetSystem library class for RISC-V using SBI eca= lls=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +#=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D =0D @@ -29,4 +31,4 @@ =0D [LibraryClasses]=0D DebugLib=0D - RiscVEdk2SbiLib=0D + RiscVSbiLib=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 1e8d53f4..8eef9fbb 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -2,6 +2,7 @@ # RISC-V SEC module.=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -52,7 +53,7 @@ RiscVCpuLib=0D RiscVOpensbiLib=0D RiscVOpensbiPlatformLib=0D - RiscVEdk2SbiLib=0D + RiscVSbiLib=0D =0D [FixedPcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/P= latform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc index 95bf5ac4..4dc24386 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc @@ -148,10 +148,10 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf=0D !endif=0D RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf=0D RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf=0D MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf=0D =0D # Flattened Device Tree (FDT) access library=0D FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 099c4e22..9dff112d 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -149,11 +149,11 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf=0D !endif=0D RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf=0D RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf=0D #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf=0D MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf=0D =0D =0D # Flattened Device Tree (FDT) access library=0D diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntim= eDxe/FvbServicesRuntimeDxe.inf b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/= RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf index 1158fe62..773b149b 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv= bServicesRuntimeDxe.inf +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv= bServicesRuntimeDxe.inf @@ -6,6 +6,7 @@ # Protocol for a RAM flash device.=0D #=0D # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -37,6 +38,7 @@ MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf index 072024dc..13c25506 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -2,6 +2,7 @@ # Library instance to create core information HOB=0D #=0D # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -38,7 +39,7 @@ MemoryAllocationLib=0D PrintLib=0D FirmwareContextProcessorSpecificLib=0D - RiscVEdk2SbiLib=0D + RiscVSbiLib=0D =0D [FixedPcd]=0D gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid=0D --=20 2.34.1