[PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector

["Zhiguang Liu" <zhiguang.liu@intel.com>]

Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table. Whether creating it or not, the highest level
page table address is fixed.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm  |  5 ++++-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb        |  3 +++
 .../ResetVector/Vtf0/X64/PageTables5L.asm     | 19 +++++++++++++++++++
 3 files changed, 26 insertions(+), 1 deletion(-)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
index 6891397c2a..b6c245e697 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
@@ -2,7 +2,7 @@
 ; @file
 ; Transition from 32 bit flat protected mode into 64 bit flat protected mode
 ;
-; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;------------------------------------------------------------------------------
@@ -18,6 +18,9 @@ Transition32FlatTo64Flat:
 
     mov     eax, cr4
     bts     eax, 5                      ; enable PAE
+%ifdef USE_5_LEVEL_PAGE_TABLE
+    bts     eax, 12                     ; Set LA57=1.
+%endif
     mov     cr4, eax
 
     mov     ecx, 0xc0000080
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 62887c4e8e..670d6a9053 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -46,6 +46,9 @@ StartOfPageTables:
     %include "X64/PageTables2M.asm"
   %endif
 %endif
+%ifdef USE_5_LEVEL_PAGE_TABLE
+  %include "X64/PageTables5L.asm"
+%endif
 EndOfPageTables:
 
 %ifdef DEBUG_PORT80
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
new file mode 100644
index 0000000000..e60e756422
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
@@ -0,0 +1,19 @@
+;------------------------------------------------------------------------------
+; @file
+; PML5 page table creation.
+;
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+    ;
+    ; PML5 table Pointers
+    ; Assume page table is create from bottom to top, and only one PML4 table there.
+    ;
+    DQ      (ADDR_OF($) - 0x1000 + PAGE_PDP_ATTR)
+
+    ;
+    ; Only first PML5 entry(first 8 bytes) pointting to a PML4 table. Others are zero
+    ;
+    TIMES   (0x1000 - 0x8) DB 0
-- 
2.31.1.windows.1