From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.65848.1680514104787179800 for ; Mon, 03 Apr 2023 02:28:24 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=BBAcDvmg; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680514104; x=1712050104; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=V6ls1ctPqM1TkuJYjOFWHOaH88WHbA+0JCB+l1mQPnc=; b=BBAcDvmgQgK06G0WCHtObcGrBmeU7OcipVStqiDGM5jAr5bw41jwxs1W +KJjtpRyMhaKIvY6MIiUKhS3vJrBuhF25lt4vcXCJZHoU/EPpH9pflADk KSozoUtqpoxSlQxOapgFTmbSnGbQouajqwGxEzohy+YYTw4TJ11rqDQlD fLpiUTv9/ABF+LIa3MbkcHYr2GwUbKoxZuNr/Ls0KXxy/mAB4Dw+XBLmO coCVyH+ax+24NVvUECiuhZO8b7k6kiVJbgxPIaycNy59eSdEZB5QkKBap gJ8czYFbSqPIg9mepylz5YC3xD6IabMrXmCJ+bhK6s6XP9WaDu3jsOb8l Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="321515139" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="321515139" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 02:28:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="688448745" X-IronPort-AV: E=Sophos;i="5.98,314,1673942400"; d="scan'208";a="688448745" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 02:28:22 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector Date: Mon, 3 Apr 2023 17:28:14 +0800 Message-Id: <20230403092814.1709-1-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. Whether creating it or not, the highest level page table address is fixed. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 5 ++++- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 3 +++ .../ResetVector/Vtf0/X64/PageTables5L.asm | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm index 6891397c2a..b6c245e697 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -2,7 +2,7 @@ ; @file ; Transition from 32 bit flat protected mode into 64 bit flat protected mode ; -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -18,6 +18,9 @@ Transition32FlatTo64Flat: mov eax, cr4 bts eax, 5 ; enable PAE +%ifdef USE_5_LEVEL_PAGE_TABLE + bts eax, 12 ; Set LA57=1. +%endif mov cr4, eax mov ecx, 0xc0000080 diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index 62887c4e8e..670d6a9053 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -46,6 +46,9 @@ StartOfPageTables: %include "X64/PageTables2M.asm" %endif %endif +%ifdef USE_5_LEVEL_PAGE_TABLE + %include "X64/PageTables5L.asm" +%endif EndOfPageTables: %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm new file mode 100644 index 0000000000..e60e756422 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm @@ -0,0 +1,19 @@ +;------------------------------------------------------------------------------ +; @file +; PML5 page table creation. +; +; Copyright (c) 2023, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + + ; + ; PML5 table Pointers + ; Assume page table is create from bottom to top, and only one PML4 table there. + ; + DQ (ADDR_OF($) - 0x1000 + PAGE_PDP_ATTR) + + ; + ; Only first PML5 entry(first 8 bytes) pointting to a PML4 table. Others are zero + ; + TIMES (0x1000 - 0x8) DB 0 -- 2.31.1.windows.1