From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.72012.1680532182181725317 for ; Mon, 03 Apr 2023 07:29:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=nuBLHz49; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 63E29B81C4E; Mon, 3 Apr 2023 14:29:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46864C4339B; Mon, 3 Apr 2023 14:29:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680532179; bh=WQSQQHgeeQOFPMzj+Kqzy8zhpaXtf63HqtHRt6AVF8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nuBLHz49r/MJMlf8Bm6EToqWa87S7x5lsSTpFZdSO08GzLeVwVIUJcHDHsBCcGy7q +f1wkVrB1UL8bm2jkMJmpJeL/Qx1FQTVuJEsHOibTuMY6QyJq6UK3OrTcfeD/MPqIo ZWDsogHAAs7u8gfp+x48wGbfcnswgVIzuLZjontXykQ6riIOgZUkt6LebgxOQobi7R U2KEU/T2eABNUm7KqEocwt8R1+hRrphuZgqysCjcoXTXIIBIPrQ+5YoEyDLQ8YCaxw Q1BqkWk4BynpqpU6mT3D/xYLb6J0yRph4kGsJeTacGy0mTHaXMXTvLcAu+k3976m9x xEWxFCkfUS7ow== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , "Ni, Ray" , Andrew Fish , "Kinney, Michael D" , "Liu, Zhiguang" , Rebecca Cran , Tom Lendacky , =?UTF-8?q?Marvin=20H=C3=A4user?= Subject: [PATCH v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Make runtime fixups XCODE-only Date: Mon, 3 Apr 2023 16:29:18 +0200 Message-Id: <20230403142920.1921619-5-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230403142920.1921619-1-ardb@kernel.org> References: <20230403142920.1921619-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The CPU exception handler library code was rewritten at some point to populate the vector code templates with absolute references at runtime, given that the XCODE linker does not permit absolute references in executable code when creating PIE executables. This is rather unfortunate, as this prevents us from using strict permissions on the memory mappings, given that the .text section needs to be writable at runtime for this arrangement to work. So let's make this hack XCODE-only, by setting a preprocessor #define from the command line when using the XCODE toolchain, and only including the runtime fixup code when the macro is defined. While at it, rename the Xcode5ExceptionHandlerAsm.nasm source file and drop the Xcode5 prefix: this code is used by other toolchains too. Signed-off-by: Ard Biesheuvel Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 5 ++++- UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf = | 4 +++- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/{Xcode5ExceptionHandlerAsm.n= asm =3D> ExceptionHandlerAsm.nasm} | 10 ++++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index d0f82095cf926e99..fdbebadab93df756 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -61,3 +61,6 @@ [LibraryClasses] MemoryAllocationLib=0D DebugLib=0D CcExitLib=0D +=0D +[BuildOptions]=0D + XCODE:*_*_X64_NASM_FLAGS =3D -D NO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 8f8a5dab79303f87..27f0b96fa9e97705 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -28,7 +28,7 @@ [Sources.Ia32] Ia32/ArchInterruptDefs.h=0D =0D [Sources.X64]=0D - X64/Xcode5ExceptionHandlerAsm.nasm=0D + X64/ExceptionHandlerAsm.nasm=0D X64/ArchExceptionHandler.c=0D X64/ArchInterruptDefs.h=0D =0D @@ -61,3 +61,5 @@ [Pcd] [FeaturePcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES=0D =0D +[BuildOptions]=0D + XCODE:*_*_X64_NASM_FLAGS =3D -D NO_ABSOLUTE_RELOCS_IN_TEXT=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHan= dlerAsm.nasm similarity index 95% rename from UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHa= ndlerAsm.nasm rename to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm= .nasm index 957478574253e619..3d64ac908010562f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -59,7 +59,11 @@ AsmIdtVectorBegin: %rep 256=0D push strict dword %[Vector] ; This instruction pushes sign-extended= 8-byte value on stack=0D push rax=0D +%ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptE= ntry)=0D +%else=0D + mov rax, ASM_PFX(CommonInterruptEntry)=0D +%endif=0D jmp rax=0D %assign Vector Vector+1=0D %endrep=0D @@ -69,8 +73,12 @@ HookAfterStubHeaderBegin: push strict dword 0 ; 0 will be fixed=0D VectorNum:=0D push rax=0D +%ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd= =0D JmpAbsoluteAddress:=0D +%else=0D + mov rax, HookAfterStubHeaderEnd=0D +%endif=0D jmp rax=0D HookAfterStubHeaderEnd:=0D mov rax, rsp=0D @@ -457,6 +465,7 @@ ASM_PFX(AsmGetTemplateAddressMap): lea rax, [HookAfterStubHeaderBegin]=0D mov qword [rcx + 0x10], rax=0D =0D +%ifdef NO_ABSOLUTE_RELOCS_IN_TEXT=0D ; Fix up CommonInterruptEntry address=0D lea rax, [ASM_PFX(CommonInterruptEntry)]=0D lea rcx, [AsmIdtVectorBegin]=0D @@ -468,6 +477,7 @@ ASM_PFX(AsmGetTemplateAddressMap): lea rax, [HookAfterStubHeaderEnd]=0D lea rcx, [JmpAbsoluteAddress]=0D mov qword [rcx - 8], rax=0D +%endif=0D =0D ret=0D =0D --=20 2.39.2