From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.79706.1680546858373903365 for ; Mon, 03 Apr 2023 11:34:18 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=OseMwUFG; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680546858; x=1712082858; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RgIJdnEcTegS5sauIw83tV0eCHBnVgOhJezIuKtn6Fk=; b=OseMwUFGmpGGruDCdRyHBYRU84wKrObu4c9MhMVIyOH77JF/JcnCMgU3 LjTxS4E4T6AtLwMqWNcPjdpqvVBpzrFXSlxmqXka2P/80hR0IwclsHGNz bSiKmF5zulDL4n/4YQTk0/yOnELCVb2MFI4PB6l9j1cmfeccK1VMlcMIt QSb5zC1nF3n6IuwB0cqL9YnAKd5OGK0JlXEm054Ca+cUjkTBUv/GcY2br 5ovwqzZ4T9/y0TCrZ9tSNiBXcT3YS0d5n36zrw+XlTHLGeKkLGZyKhu2d 9N0wQSi0ehoYQxEW91wV1bmpPNRpdoVU6EJH5Ns5TGX0WMSlCOKw6oWpJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="404740505" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="404740505" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 11:34:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="1015820786" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="1015820786" Received: from cchiu4-mobl.gar.corp.intel.com ([10.251.25.144]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 11:34:17 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni , Ted Kuo Subject: [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. Date: Mon, 3 Apr 2023 11:34:05 -0700 Message-Id: <20230403183405.1689-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu Reviewed-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 46 ++++++++++++++++++++++= ++---------------------- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 45 ++++++++++++++++++++++= ++--------------------- 2 files changed, 48 insertions(+), 43 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..900126b93b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): cmp esp, 0=0D jz ParamError=0D =0D + ;=0D + ; If microcode already loaded before this function, exit this function = with SUCCESS.=0D + ;=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + xor eax, eax ; Clear EAX=0D + xor edx, edx ; Clear EDX=0D + wrmsr ; Load 0 to MSR at 8Bh=0D +=0D + mov eax, 1=0D + cpuid=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + rdmsr ; Get current microcode signature=0D + xor eax, eax=0D + test edx, edx=0D + jnz Exit2=0D +=0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D ; first check UPD header revision=0D @@ -330,7 +346,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]=0D jne LoadMicrocodeDefault1=0D test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]=0D - jnz LoadCheck ; Jif signature and platform ID match=0D + jnz LoadMicrocode ; Jif signature and platform ID match=0D =0D LoadMicrocodeDefault1:=0D ; Check if extended header exists=0D @@ -363,7 +379,7 @@ CheckExtSig: cmp dword [edi + ExtSig.ExtSigProcessor], ebx=0D jne LoadMicrocodeDefault2=0D test dword [edi + ExtSig.ExtSigFlags], edx=0D - jnz LoadCheck ; Jif signature and platform ID match=0D + jnz LoadMicrocode ; Jif signature and platform ID match=0D LoadMicrocodeDefault2:=0D ; Check if any more extended signatures exist=0D add edi, ExtSig.size=0D @@ -435,23 +451,7 @@ LoadMicrocodeDefault4: ; Is valid Microcode start point ?=0D cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh=0D jz Done=0D -=0D -LoadCheck:=0D - ; Get the revision of the current microcode update loaded=0D - mov ecx, MSR_IA32_BIOS_SIGN_ID=0D - xor eax, eax ; Clear EAX=0D - xor edx, edx ; Clear EDX=0D - wrmsr ; Load 0 to MSR at 8Bh=0D -=0D - mov eax, 1=0D - cpuid=0D - mov ecx, MSR_IA32_BIOS_SIGN_ID=0D - rdmsr ; Get current microcode signature=0D -=0D - ; Verify this microcode update is not already loaded=0D - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx=0D - je Continue=0D -=0D + jmp CheckMainHeader=0D LoadMicrocode:=0D ; EAX contains the linear address of the start of the Update Data=0D ; EDX contains zero=0D @@ -465,10 +465,12 @@ LoadMicrocode: mov eax, 1=0D cpuid=0D =0D -Continue:=0D - jmp NextMicrocode=0D -=0D Done:=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + xor eax, eax ; Clear EAX=0D + xor edx, edx ; Clear EDX=0D + wrmsr ; Load 0 to MSR at 8Bh=0D +=0D mov eax, 1=0D cpuid=0D mov ecx, MSR_IA32_BIOS_SIGN_ID=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index b32fa32a89..698bb063a7 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError=0D mov rsp, rcx=0D =0D + ;=0D + ; If microcode already loaded before this function, exit this function = with SUCCESS.=0D + ;=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + xor eax, eax ; Clear EAX=0D + xor edx, edx ; Clear EDX=0D + wrmsr ; Load 0 to MSR at 8Bh=0D +=0D + mov eax, 1=0D + cpuid=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + rdmsr ; Get current microcode signature=0D + xor rax, rax=0D + test edx, edx=0D + jnz Exit2=0D +=0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D ; first check UPD header revision=0D @@ -198,7 +214,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]=0D jne LoadMicrocodeDefault1=0D test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]=0D - jnz LoadCheck ; Jif signature and platform ID match=0D + jnz LoadMicrocode ; Jif signature and platform ID match=0D =0D LoadMicrocodeDefault1:=0D ; Check if extended header exists=0D @@ -231,7 +247,7 @@ CheckExtSig: cmp dword [edi + ExtSig.ExtSigProcessor], ebx=0D jne LoadMicrocodeDefault2=0D test dword [edi + ExtSig.ExtSigFlags], edx=0D - jnz LoadCheck ; Jif signature and platform ID match=0D + jnz LoadMicrocode ; Jif signature and platform ID match=0D LoadMicrocodeDefault2:=0D ; Check if any more extended signatures exist=0D add edi, ExtSig.size=0D @@ -276,22 +292,7 @@ LoadMicrocodeDefault4: ; Is valid Microcode start point ?=0D cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh=0D jz Done=0D -=0D -LoadCheck:=0D - ; Get the revision of the current microcode update loaded=0D - mov ecx, MSR_IA32_BIOS_SIGN_ID=0D - xor eax, eax ; Clear EAX=0D - xor edx, edx ; Clear EDX=0D - wrmsr ; Load 0 to MSR at 8Bh=0D -=0D - mov eax, 1=0D - cpuid=0D - mov ecx, MSR_IA32_BIOS_SIGN_ID=0D - rdmsr ; Get current microcode signature=0D -=0D - ; Verify this microcode update is not already loaded=0D - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx=0D - je Continue=0D + jmp CheckMainHeader=0D =0D LoadMicrocode:=0D ; EAX contains the linear address of the start of the Update Data=0D @@ -306,10 +307,12 @@ LoadMicrocode: mov eax, 1=0D cpuid=0D =0D -Continue:=0D - jmp NextMicrocode=0D -=0D Done:=0D + mov ecx, MSR_IA32_BIOS_SIGN_ID=0D + xor eax, eax ; Clear EAX=0D + xor edx, edx ; Clear EDX=0D + wrmsr ; Load 0 to MSR at 8Bh=0D +=0D mov eax, 1=0D cpuid=0D mov ecx, MSR_IA32_BIOS_SIGN_ID=0D --=20 2.35.0.windows.1