From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.107004.1680626644810205254 for ; Tue, 04 Apr 2023 09:44:06 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=BO8EJr0u; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680626646; x=1712162646; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+CYqfLx9Og59bLlZNot0oArgdfBHmHCbxfmYWsv5NWM=; b=BO8EJr0ugjxodfPVC0VOC7OHg3o//ZpltMdZag34Ugmza57+3zUbsRcd keIqf/Gs+8slE7B0ImXMr3Qq8Whj07nuUL1fXH3Wfmfz1keuXzTP/lE+1 wOIA2yfqZvm3ktXcc+31XBUM0KTgqZxT7BR9OeMjq54nAzUgyqB/h6yAs NdULWoWHtKt7mTJKiSNvTrBlAycvcnaJqKNSx77yE8D8bDkXSMdNhHGwE yDVYKHgn//DkwN1NkyMJJgQv+eWwBAG5Dn14bnThq0KgYSwKr12ynG3Bn /5fDKTzFDW9ZXR3ULvMgUwS5gToCgses/zSha4obApm8FV7ZH1UgunIUV A==; X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="428527784" X-IronPort-AV: E=Sophos;i="5.98,318,1673942400"; d="scan'208";a="428527784" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 09:44:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="750987396" X-IronPort-AV: E=Sophos;i="5.98,318,1673942400"; d="scan'208";a="750987396" Received: from awarkent-mobl1.amr.corp.intel.com ([10.212.50.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 09:44:05 -0700 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Sunil V L Subject: [PATCH v6 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Date: Tue, 4 Apr 2023 11:43:59 -0500 Message-Id: <20230404164359.25852-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230404164359.25852-1-andrei.warkentin@intel.com> References: <20230404164359.25852-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Reviewed-by: Sunil V L Signed-off-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af596..0e2a5785e8a4 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ [LibraryClasses] FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe40..7c7650f0d298 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index adf73f2eb66c..b35c77774510 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // -- 2.25.1