From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.11524.1680881422763786107 for ; Fri, 07 Apr 2023 08:30:23 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=softfail (domain: linaro.org, ip: 213.251.184.221, mailfrom: marcin.juszkiewicz@linaro.org) Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 6CBA9260FDE; Fri, 7 Apr 2023 17:30:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at juszkiewicz.com.pl Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DJ_aKFOEHeIK; Fri, 7 Apr 2023 17:30:15 +0200 (CEST) Received: from applejack.lan (83.11.21.111.ipv4.supernova.orange.pl [83.11.21.111]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id 9A2A5260FEB; Fri, 7 Apr 2023 17:30:13 +0200 (CEST) From: "Marcin Juszkiewicz" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Rebecca Cran , Pedro Falcato , Marcin Juszkiewicz Subject: [PATCH v5 2/2] add ArmCpuInfo EFI application Date: Fri, 7 Apr 2023 17:29:57 +0200 Message-Id: <20230407152957.157494-3-marcin.juszkiewicz@linaro.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230407152957.157494-1-marcin.juszkiewicz@linaro.org> References: <1753ABF1A296B040.11304@groups.io> <20230407152957.157494-1-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable App goes through ID_AA64*_EL1 system registers and decode their values. Signed-off-by: Marcin Juszkiewicz --- ArmPkg/ArmPkg.dsc | 1 + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 38 + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2319 ++++++++++++++++++ 3 files changed, 2358 insertions(+) create mode 100644 ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf create mode 100644 ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index 3fb95d1951a9..6b938ce8b671 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -166,6 +166,7 @@ [Components.AARCH64] ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf =20 [Components.AARCH64, Components.ARM] ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf b/ArmPkg/Applic= ation/ArmCpuInfo/ArmCpuInfo.inf new file mode 100644 index 000000000000..c6f634cd01b7 --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf @@ -0,0 +1,38 @@ +## @file +# +# Attempt to have AArch64 cpu information. +# +# Based on HelloWorld: +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved. +# Copyright (c) 2023 Marcin Juszkiewicz +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmCpuInfo + FILE_GUID =3D b3134491-6502-4faf-a9da-007184e3216= 3 + MODULE_TYPE =3D UEFI_APPLICATION + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UefiMain + +# +# This flag specifies whether HII resource section is generated into PE= image. +# + UEFI_HII_RESOURCE_SECTION =3D TRUE + +[Sources] + ArmCpuInfo.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + ArmLib + UefiApplicationEntryPoint + UefiLib diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Applicat= ion/ArmCpuInfo/ArmCpuInfo.c new file mode 100644 index 000000000000..2fc12059f727 --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c @@ -0,0 +1,2319 @@ +/** @file + + Copyright (c) 2023 Marcin Juszkiewicz + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include + +VOID +PrintText ( + CONST CHAR8 *field, + CONST CHAR8 *Bits, + CONST CHAR8 *Value, + CONST CHAR8 *Description + ) +{ + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, Bits, Value, Descripti= on); +} + +VOID +PrintValues ( + CONST CHAR8 *field, + CONST CHAR8 *Bits, + CONST UINT8 Value, + CONST CHAR8 *Description + ) +{ + STATIC CONST CHAR8 binaries[][5] =3D { + "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", + "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111" + }; + + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, Bits, binaries[Value &= 0xf], Description); +} + +VOID +PrintSpacer ( + VOID + ) +{ + AsciiPrint ("------------------|-------|-------|----------------------= ------------------------\n"); +} + +VOID +HandleAa64Mmfr0 ( + CONST UINT64 Aa64Mmfr0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D Aa64Mmfr0 & 0xf; + switch (Value) { + case 0b0000: + Description =3D "32 Bits (4GB) of physical address range supporte= d."; + break; + case 0b0001: + Description =3D "36 Bits (64GB) of physical address range support= ed."; + break; + case 0b0010: + Description =3D "40 Bits (1TB) of physical address range supporte= d."; + break; + case 0b0011: + Description =3D "42 Bits (4TB) of physical address range supporte= d."; + break; + case 0b0100: + Description =3D "44 Bits (16TB) of physical address range support= ed."; + break; + case 0b0101: + Description =3D "48 Bits (256TB) of physical address range suppor= ted."; + break; + case 0b0110: + Description =3D "52 Bits (4PB) of physical address range supporte= d."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + if (Value =3D=3D 0b0110) { + PrintText ("", "", "", "FEAT_LPA implemented."); + } + + Bits =3D "7:4 "; + Value =3D (Aa64Mmfr0 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "ASID: 8 Bits"; + break; + case 0b0010: + Description =3D "ASID: 16 Bits"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Mmfr0 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "No mixed-endian support."; + break; + case 0b0001: + Description =3D "Mixed-endian support."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // only valid for BigEnd !=3D 0b0000 + if (((Aa64Mmfr0 >> 8) & 0xf) !=3D 0b0000 ) { + if (((Aa64Mmfr0 >> 16) & 0xf) =3D=3D 0b0000 ) { + PrintValues ("ID_AA64MMFR0", "19:16", 0b0000, "No mixed-endian sup= port at EL0."); + } + + if (((Aa64Mmfr0 >> 16) & 0xf) =3D=3D 0b0001 ) { + PrintValues ("ID_AA64MMFR0", "19:16", 0b0001, "Mixed-endian suppor= t at EL0."); + } + } + + Bits =3D "15:12"; + Value =3D (Aa64Mmfr0 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "No support for a distinction between Secure and N= on-Secure Memory."; + break; + case 0b0001: + Description =3D "Supports a distinction between Secure and Non-Sec= ure Memory."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Mmfr0 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D " 4KB granule supported."; + break; + case 0b1111: + Description =3D " 4KB granule not supported."; + break; + case 0b0001: // add FEAT_LPA2 check + Description =3D " 4KB granule supported for 52-bit address."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Mmfr0 >> 40) & 0xf; + switch (Value) { + case 0b0001: + Description =3D " 4KB granule not supported at stage 2."; + break; + case 0b0010: + Description =3D " 4KB granule supported at stage 2."; + break; + case 0b0011: + Description =3D " 4KB granule supported at stage 2 for 52-bit addr= ess."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Mmfr0 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "16KB granule not supported."; + break; + case 0b0001: + Description =3D "16KB granule supported."; + break; + case 0b0010: // add FEAT_LPA2 check + Description =3D "16KB granule supported for 52-bit address."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Mmfr0 >> 32) & 0xf; + switch (Value) { + case 0b0001: + Description =3D "16KB granule not supported at stage 2."; + break; + case 0b0010: + Description =3D "16KB granule supported at stage 2."; + break; + case 0b0011: + Description =3D "16KB granule supported at stage 2 for 52-bit addr= ess."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Mmfr0 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "64KB granule supported."; + break; + case 0b1111: + Description =3D "64KB granule not supported."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Mmfr0 >> 36) & 0xf; + switch (Value) { + case 0b0001: + Description =3D "64KB granule not supported at stage 2."; + break; + case 0b0010: + Description =3D "64KB granule supported at stage 2."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Mmfr0 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_ExS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_ExS implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 55:48 reserved + + Bits =3D "59:56"; + Value =3D (Aa64Mmfr0 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_FGT not implemented."; + break; + case 0b0001: + Description =3D "FEAT_FGT implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "63:60"; + Value =3D (Aa64Mmfr0 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_ECV not implemented."; + break; + case 0b0001: + Description =3D "FEAT_ECV implemented."; + break; + case 0b0010: + Description =3D "FEAT_ECV implemented with extras."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +VOID +HandleAa64Mmfr1 ( + CONST UINT64 Aa64Mmfr1, + CONST UINT64 Aa64Pfr0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR1"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D Aa64Mmfr1 & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_HAFDBS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_HAFDBS implemented without dirty status supp= ort."; + break; + case 0b0010: + Description =3D "FEAT_HAFDBS implemented with dirty status support= ."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Mmfr1 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_VMID16 not implemented."; + break; + case 0b0010: + Description =3D "FEAT_VMID16 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Mmfr1 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_VHE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_VHE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Mmfr1 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_HPDS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_HPDS implemented."; + break; + case 0b0010: + Description =3D "FEAT_HPDS2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Mmfr1 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LOR not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LOR implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Mmfr1 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_PAN not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PAN implemented."; + break; + case 0b0010: + Description =3D "FEAT_PAN2 implemented."; + break; + case 0b0011: + Description =3D "FEAT_PAN3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // when FEAT_RAS implemented + if ((((Aa64Pfr0 >> 28) & 0xf) =3D=3D 0b0001) || + (((Aa64Pfr0 >> 28) & 0xf) =3D=3D 0b0010)) + { + if (((Aa64Mmfr1 >> 24) & 0xf) =3D=3D 0b0000 ) { + PrintValues ("ID_AA64MMFR1", "27:24", 0b0000, "The PE never genera= tes an SError interrupt due to"); + PrintText ("", "", "", "an External abort on a speculative read.")= ; + } + + if (((Aa64Mmfr1 >> 24) & 0xf) =3D=3D 0b0001 ) { + PrintValues ("ID_AA64MMFR1", "27:24", 0b0001, "The PE might genera= te an SError interrupt due to"); + PrintText ("", "", "", "an External abort on a speculative read.")= ; + } + } + + Bits =3D "31:28"; + Value =3D (Aa64Mmfr1 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_XNX not implemented."; + break; + case 0b0001: + Description =3D "FEAT_XNX implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Mmfr1 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TWED not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TWED implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Mmfr1 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_ETS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_ETS implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Mmfr1 >> 40) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_HCX not implemented."; + break; + case 0b0001: + Description =3D "FEAT_HCX implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Mmfr1 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_AFP not implemented."; + break; + case 0b0001: + Description =3D "FEAT_AFP implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "51:48"; + Value =3D (Aa64Mmfr1 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_nTLBPA not implemented."; + break; + case 0b0001: + Description =3D "FEAT_nTLBPA implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Mmfr1 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TIDCP1 not implemented"; + break; + case 0b0001: + Description =3D "FEAT_TIDCP1 implemented"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Mmfr1 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_CMOW not implemented."; + break; + case 0b0001: + Description =3D "FEAT_CMOW implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 63:60 reserved +} + +VOID +HandleAa64Mmfr2 ( + CONST UINT64 Aa64Mmfr2 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR2"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D (Aa64Mmfr2) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TTCNP not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TTCNP implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Mmfr2 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_UAO not implemented."; + break; + case 0b0001: + Description =3D "FEAT_UAO implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Mmfr2 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LSMAOC not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LSMAOC implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Mmfr2 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_IESB not implemented."; + break; + case 0b0001: + Description =3D "FEAT_IESB implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Mmfr2 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LVA not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LVA implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Mmfr2 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_CCIDX not implemented."; + break; + case 0b0001: + Description =3D "FEAT_CCIDX implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Mmfr2 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_NV not implemented."; + break; + case 0b0001: + Description =3D "FEAT_NV implemented."; + break; + case 0b0010: + Description =3D "FEAT_NV2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Mmfr2 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TTST not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TTST implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Mmfr2 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LSE2 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LSE2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Mmfr2 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_IDST not implemented."; + break; + case 0b0001: + Description =3D "FEAT_IDST implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Mmfr2 >> 40) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_S2FWB not implemented."; + break; + case 0b0001: + Description =3D "FEAT_S2FWB implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 47:44 reserved + + Bits =3D "51:48"; + Value =3D (Aa64Mmfr2 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TTL not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TTL implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Mmfr2 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_BBM: Level 0 support for changing block size= is supported."; + break; + case 0b0001: + Description =3D "FEAT_BBM: Level 1 support for changing block size= is supported."; + break; + case 0b0010: + Description =3D "FEAT_BBM: Level 2 support for changing block size= is supported."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Mmfr2 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_EVT not implemented."; + break; + case 0b0001: + Description =3D "FEAT_EVT: HCR_EL2.{TOCU, TICAB, TID4} traps are s= upported."; + break; + case 0b0010: + Description =3D "FEAT_EVT: HCR_EL2.{TTLBOS, TTLSBIS, TOCU, TICAB, = TID4} traps are supported."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "63:60"; + Value =3D (Aa64Mmfr2 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_E0PD not implemented."; + break; + case 0b0001: + Description =3D "FEAT_E0PD implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +VOID +HandleAa64Pfr0 ( + CONST UINT64 Aa64Pfr0, + CONST UINT64 Aa64Pfr1 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D (Aa64Pfr0) & 0xf; + switch (Value) { + case 0b0001: + Description =3D "EL0 in AArch64 only"; + break; + case 0b0010: + Description =3D "EL0 in AArch64 and AArch32"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Pfr0 >> 4) & 0xf; + switch (Value) { + case 0b0001: + Description =3D "EL1 in AArch64 only"; + break; + case 0b0010: + Description =3D "EL1 in AArch64 and AArch32"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Pfr0 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "EL2 not implemented."; + break; + case 0b0001: + Description =3D "EL2 in AArch64 only"; + break; + case 0b0010: + Description =3D "EL2 in AArch64 and AArch32"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Pfr0 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "EL3 not implemented."; + break; + case 0b0001: + Description =3D "EL3 in AArch64 only"; + break; + case 0b0010: + Description =3D "EL3 in AArch64 and AArch32"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Pfr0 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Floating-point implemented."; + break; + case 0b0001: + Description =3D "Floating-point with half-precision support (FEAT= _FP16)."; + break; + case 0b1111: + Description =3D "Floating-point not implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Pfr0 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Advanced SIMD implemented."; + break; + case 0b0001: + Description =3D "Advanced SIMD with half precision support (FEAT_= FP16)."; + break; + case 0b1111: + Description =3D "Advanced SIMD not implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Pfr0 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "System registers of GIC CPU not implemented."; + break; + case 0b0001: + Description =3D "System registers to versions 3.0/4.0 of GIC CPU i= mplemented."; + break; + case 0b0011: + Description =3D "System registers to versions 4.1 of GIC CPU imple= mented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Pfr0 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RAS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_RAS implemented."; + break; + case 0b0010: + Description =3D "FEAT_RASv1p1 implemented."; + // 0b0010 FEAT_RASv1p1 implemented and, if EL3 is implemented, FEA= T_DoubleFault implemented. + if ((((Aa64Pfr0 >> 12) & 0xf) =3D=3D 0b0001) || + (((Aa64Pfr0 >> 12) & 0xf) =3D=3D 0b0010)) + { + Description =3D "FEAT_RASv1p1 implemented. FEAT_DoubleFault impl= emented."; + } + + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Pfr0 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SVE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SVE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Pfr0 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Secure EL2 not implemented."; + break; + case 0b0001: + Description =3D "Secure EL2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Pfr0 >> 40) & 0xf; + switch (Value) { + case 0b0000: + if (((Aa64Pfr1 >> 16) & 0xf) =3D=3D 0b0000 ) { + Description =3D "FEAT_MPAM not implemented."; + } + + if (((Aa64Pfr1 >> 16) & 0xf) =3D=3D 0b0001 ) { + Description =3D "FEAT_MPAM v0.1 implemented."; + } + + break; + case 0b0001: + if (((Aa64Pfr1 >> 16) & 0xf) =3D=3D 0b0000 ) { + Description =3D "FEAT_MPAM v1.0 implemented."; + } + + if (((Aa64Pfr1 >> 16) & 0xf) =3D=3D 0b0001 ) { + Description =3D "FEAT_MPAM v1.1 implemented."; + } + + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Pfr0 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_AMU not implemented."; + break; + case 0b0001: + Description =3D "FEAT_AMUv1 implemented."; + break; + case 0b0010: + Description =3D "FEAT_AMUv1p1 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "51:48"; + Value =3D (Aa64Pfr0 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_DIT not implemented."; + break; + case 0b0001: + Description =3D "FEAT_DIT implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Pfr0 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RME not implemented"; + break; + case 0b0001: + Description =3D "FEAT_RME implemented"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Pfr0 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "no info is FEAT_CSV2 implemented."; + break; + case 0b0001: + Description =3D "FEAT_CSV2 implemented."; + break; + case 0b0010: + Description =3D "FEAT_CSV2_2 implemented."; + break; + case 0b0011: + Description =3D "FEAT_CSV2_3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + if (Value =3D=3D 0b0001) { + if (((Aa64Pfr1 >> 32) & 0xf) =3D=3D 0b0001 ) { + PrintValues ("ID_AA64PRF1", "35:32", 0b0001, "FEAT_CSV2_1p1 implem= ented."); + } + + if (((Aa64Pfr1 >> 32) & 0xf) =3D=3D 0b0010 ) { + PrintValues ("ID_AA64PRF1", "35:32", 0b0010, "FEAT_CSV2_1p2 implem= ented."); + } + } + + Bits =3D "63:60"; + Value =3D (Aa64Pfr0 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_CSV3 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_CSV3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +VOID +HandleAa64Pfr1 ( + CONST UINT64 Aa64Pfr1 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR1"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D Aa64Pfr1 & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_BTI not implemented."; + break; + case 0b0001: + Description =3D "FEAT_BTI implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Pfr1 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SSBS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SSBS implemented."; + break; + case 0b0010: + Description =3D "FEAT_SSBS2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Pfr1 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_MTE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_MTE implemented."; + break; + case 0b0010: + Description =3D "FEAT_MTE2 implemented."; + break; + case 0b0011: + Description =3D "FEAT_MTE3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 15:12 is RAS_frac + // 19:16 is MPAM_frac + // 23:20 is reserved + + Bits =3D "27:24"; + Value =3D (Aa64Pfr1 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SME not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SME implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Pfr1 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RNG_TRAP not implemented."; + break; + case 0b0001: + Description =3D "FEAT_RNG_TRAP implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 35:32 is CSV2_frac + + Bits =3D "39:36"; + Value =3D (Aa64Pfr1 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_NMI not implemented."; + break; + case 0b0001: + Description =3D "FEAT_NMI implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 63:40 are reserved +} + +VOID +HandleAa64Isar0 ( + CONST UINT64 Aa64Isar0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + // 3:0 reserved + + Bits =3D "7:4 "; + Value =3D (Aa64Isar0 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_AES, FEAT_PMULL not implemented."; + break; + case 0b0001: + Description =3D "FEAT_AES implemented."; + break; + case 0b0010: + Description =3D "FEAT_AES and FEAT_PMULL implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Isar0 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SHA1 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SHA1 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Isar0 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SHA256, FEAT_SHA512 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SHA256 implemented."; + break; + case 0b0010: + Description =3D "FEAT_SHA512 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Isar0 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "CRC32 not implemented."; + break; + case 0b0001: + Description =3D "CRC32 instructions implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Isar0 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LSE not implemented."; + break; + case 0b0010: + Description =3D "FEAT_LSE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Isar0 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "TME instructions not implemented."; + break; + case 0b0001: + Description =3D "TME instructions implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Isar0 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RDM not implemented."; + break; + case 0b0001: + Description =3D "FEAT_RDM implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Isar0 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SHA3 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SHA3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Isar0 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SM3 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SM3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Isar0 >> 40) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SM4 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SM4 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Isar0 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_DotProd not implemented."; + break; + case 0b0001: + Description =3D "FEAT_DotProd implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "51:48"; + Value =3D (Aa64Isar0 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_FHM not implemented."; + break; + case 0b0001: + Description =3D "FEAT_FHM implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Isar0 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_FlagM/FEAT_FlagM2 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_FlagM implemented."; + break; + case 0b0010: + Description =3D "FEAT_FlagM2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Isar0 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TLBIOS/FEAT_TLBIRANGE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TLBIOS implemented."; + break; + case 0b0010: + Description =3D "FEAT_TLBIRANGE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "63:60"; + Value =3D (Aa64Isar0 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RNG not implemented."; + break; + case 0b0001: + Description =3D "FEAT_RNG implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +VOID +HandleAa64Isar1 ( + CONST UINT64 Aa64Isar1 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR1"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D (Aa64Isar1 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "DC CVAP not implemented."; + break; + case 0b0001: + Description =3D "FEAT_DPB implemented."; + break; + case 0b0010: + Description =3D "FEAT_DPB2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Isar1 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Address Authentication (APA) not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + Description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + Description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + Description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + Description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + if (Value > 0) { + PrintText ("", "", "", "FEAT_PACQARMA5 implemented."); + } + + Bits =3D "11:8 "; + Value =3D (Aa64Isar1 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Address Authentication (API) not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + Description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + Description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + Description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + Description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + if (Value > 0) { + PrintText ("", "", "", "FEAT_PACIMP implemented."); + } + + Bits =3D "15:12"; + Value =3D (Aa64Isar1 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_JSCVT not implemented."; + break; + case 0b0001: + Description =3D "FEAT_JSCVT implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Isar1 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_FCMA not implemented."; + break; + case 0b0001: + Description =3D "FEAT_FCMA implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Isar1 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LRCPC (2) not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LRCPC implemented."; + break; + case 0b0010: + Description =3D "FEAT_LRCPC2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Isar1 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_PACQARMA5 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PACQARMA5 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "31:28"; + Value =3D (Aa64Isar1 >> 28) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_PACIMP not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PACIMP implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Isar1 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_FRINTTS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_FRINTTS implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Isar1 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SB not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SB implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Isar1 >> 40) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SPECRES not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SPECRES implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Isar1 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_BF16 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_BF16 implemented."; + break; + case 0b0010: + Description =3D "FEAT_EBF16 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "51:48"; + Value =3D (Aa64Isar1 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_DGH not implemented."; + break; + case 0b0001: + Description =3D "FEAT_DGH implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Isar1 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_I8MM not implemented."; + break; + case 0b0001: + Description =3D "FEAT_I8MM implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Isar1 >> 56) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_XS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_XS implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "63:60"; + Value =3D (Aa64Isar1 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_LS64 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_LS64 implemented."; + break; + case 0b0010: + Description =3D "FEAT_LS64_V implemented."; + break; + case 0b0011: + Description =3D "FEAT_LS64_ACCDATA implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +VOID +HandleAa64Isar2 ( + CONST UINT64 Aa64Isar2 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR2"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D (Aa64Isar2 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_WFxT not implemented."; + break; + case 0b0010: + Description =3D "FEAT_WFxT implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Isar2 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_RPRES not implemented."; + break; + case 0b0001: + Description =3D "FEAT_RPRES implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Isar2 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_PACQARMA3 not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PACQARMA3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Isar2 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Address Authentication (APA3) not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + Description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + Description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + Description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + Description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "19:16"; + Value =3D (Aa64Isar2 >> 16) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_MOPS not implemented."; + break; + case 0b0001: + Description =3D "FEAT_MOPS implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Isar2 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_HBC not implemented."; + break; + case 0b0001: + Description =3D "FEAT_HBC implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "27:24"; + Value =3D (Aa64Isar2 >> 24) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_CONSTPACFIELD not implemented."; + break; + case 0b0001: + Description =3D "FEAT_CONSTPACFIELD implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 63:28 reserved +} + +VOID +HandleAa64Dfr0 ( + CONST UINT64 Aa64Dfr0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64DFR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D (Aa64Dfr0 >> 4) & 0xf; + switch (Value) { + case 0b0110: + Description =3D "Armv8 debug architecture"; + break; + case 0b0111: + Description =3D "Armv8 debug architecture with VHE"; + break; + case 0b1000: + Description =3D "FEAT_Debugv8p2 implemented."; + break; + case 0b1001: + Description =3D "FEAT_Debugv8p4 implemented."; + break; + case 0b1010: + Description =3D "FEAT_Debugv8p8 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Dfr0 >> 4) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Trace unit System registers not implemented."; + break; + case 0b0001: + Description =3D "Trace unit System registers implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "11:8 "; + Value =3D (Aa64Dfr0 >> 8) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Performance Monitors Extension not implemented."; + break; + case 0b0001: + Description =3D "FEAT_PMUv3 implemented."; + break; + case 0b0100: + Description =3D "FEAT_PMUv3p1 implemented."; + break; + case 0b0101: + Description =3D "FEAT_PMUv3p4 implemented."; + break; + case 0b0110: + Description =3D "FEAT_PMUv3p5 implemented."; + break; + case 0b0111: + Description =3D "FEAT_PMUv3p7 implemented."; + break; + case 0b1000: + Description =3D "FEAT_PMUv3p8 implemented."; + break; + case 0b1111: + Description =3D "IMPLEMENTATION DEFINED form of performance monito= rs supported."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "15:12"; + Value =3D (Aa64Dfr0 >> 12) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "reserved"; + break; + default: + Description =3D "Number of breakpoints, minus 1."; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 19:16 reserved + + Bits =3D "23:20"; + Value =3D (Aa64Dfr0 >> 20) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "reserved"; + break; + default: + Description =3D "Number of watchpoints, minus 1."; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 27:24 reserved + + Bits =3D "31:28"; + Value =3D (Aa64Dfr0 >> 28) & 0xf; + switch (Value) { + default: + Description =3D "Number of breakpoints that are context-aware, min= us 1."; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "35:32"; + Value =3D (Aa64Dfr0 >> 32) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_SPE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_SPE implemented."; + break; + case 0b0010: + Description =3D "FEAT_SPEv1p1 implemented."; + break; + case 0b0011: + Description =3D "FEAT_SPEv1p2 implemented."; + break; + case 0b0100: + Description =3D "FEAT_SPEv1p3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Dfr0 >> 36) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_DoubleLock implemented."; + break; + case 0b1111: + Description =3D "FEAT_DoubleLock not implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "43:40"; + Value =3D (Aa64Dfr0 >> 40) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TRF not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TRF implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Dfr0 >> 44) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_TRBE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_TRBE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "51:48"; + Value =3D (Aa64Dfr0 >> 48) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_MTPMU not implemented."; + break; + case 0b0001: + Description =3D "FEAT_MTPMU and FEAT_PMUv3 implemented."; + break; + case 0b1111: + Description =3D "FEAT_MTPMU not implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "55:52"; + Value =3D (Aa64Dfr0 >> 52) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "FEAT_BRBE not implemented."; + break; + case 0b0001: + Description =3D "FEAT_BRBE implemented."; + break; + case 0b0010: + Description =3D "FEAT_BRBEv1p1 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 59:56 reserved + + Bits =3D "63:60"; + Value =3D (Aa64Dfr0 >> 60) & 0xf; + switch (Value) { + case 0b0000: + Description =3D "Setting MDCR_EL2.HPMN to zero has CONSTRAINED UNP= REDICTABLE behavior."; + break; + case 0b0001: + Description =3D "FEAT_HPMN0 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +EFI_STATUS +EFIAPI +UefiMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT64 Aa64Dfr0; + UINT64 Aa64Isar0; + UINT64 Aa64Isar1; + UINT64 Aa64Isar2; + UINT64 Aa64Mmfr0; + UINT64 Aa64Mmfr1; + UINT64 Aa64Mmfr2; + UINT64 Aa64Pfr0; + UINT64 Aa64Pfr1; + + Aa64Dfr0 =3D ArmReadIdAA64Dfr0 (); + Aa64Isar0 =3D ArmReadIdAA64Isar0 (); + Aa64Isar1 =3D ArmReadIdAA64Isar1 (); + Aa64Isar2 =3D ArmReadIdAA64Isar2 (); + Aa64Mmfr0 =3D ArmReadIdAA64Mmfr0 (); + Aa64Mmfr1 =3D ArmReadIdAA64Mmfr1 (); + Aa64Mmfr2 =3D ArmReadIdAA64Mmfr2 (); + Aa64Pfr0 =3D ArmReadIdAA64Pfr0 (); + Aa64Pfr1 =3D ArmReadIdAA64Pfr1 (); + + AsciiPrint ("ID_AA64MMFR0_EL1 =3D 0x%016lx\n", Aa64Mmfr0); + AsciiPrint ("ID_AA64MMFR1_EL1 =3D 0x%016lx\n", Aa64Mmfr1); + AsciiPrint ("ID_AA64MMFR2_EL1 =3D 0x%016lx\n", Aa64Mmfr2); + AsciiPrint ("ID_AA64PFR0_EL1 =3D 0x%016lx\n", Aa64Pfr0); + AsciiPrint ("ID_AA64PFR1_EL1 =3D 0x%016lx\n", Aa64Pfr1); + AsciiPrint ("ID_AA64ISAR0_EL1 =3D 0x%016lx\n", Aa64Isar0); + AsciiPrint ("ID_AA64ISAR1_EL1 =3D 0x%016lx\n", Aa64Isar1); + AsciiPrint ("ID_AA64ISAR2_EL1 =3D 0x%016lx\n", Aa64Isar2); + AsciiPrint ("ID_AA64DFR0_EL1 =3D 0x%016lx\n", Aa64Dfr0); + + AsciiPrint ("\n"); + PrintText ("Register", "Bits", "Value", "Feature"); + PrintSpacer (); + + HandleAa64Mmfr0 (Aa64Mmfr0); + PrintSpacer (); + HandleAa64Mmfr1 (Aa64Mmfr1, Aa64Pfr0); + PrintSpacer (); + HandleAa64Mmfr2 (Aa64Mmfr2); + + PrintSpacer (); + HandleAa64Pfr0 (Aa64Pfr0, Aa64Pfr1); + PrintSpacer (); + HandleAa64Pfr1 (Aa64Pfr1); + + PrintSpacer (); + HandleAa64Isar0 (Aa64Isar0); + PrintSpacer (); + HandleAa64Isar1 (Aa64Isar1); + PrintSpacer (); + HandleAa64Isar2 (Aa64Isar2); + + PrintSpacer (); + HandleAa64Dfr0 (Aa64Dfr0); + + return EFI_SUCCESS; +} --=20 2.40.0