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From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: devel@edk2.groups.io
Cc: Andrei Warkentin <andrei.warkentin@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH v7 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec
Date: Fri,  7 Apr 2023 16:44:25 -0500	[thread overview]
Message-ID: <20230407214425.4360-4-andrei.warkentin@intel.com> (raw)
In-Reply-To: <20230407214425.4360-1-andrei.warkentin@intel.com>

If the SerialPortLib had any initialization needed, this
would be skipped in the RiscVVirt Sec. Follow the example
seen elsewhere (ArmVirtPkg PrePi).

Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec,
yet using DBCN elsewhere.

Cc: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
 OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
 OvmfPkg/RiscVVirt/Sec/SecMain.h   | 1 +
 OvmfPkg/RiscVVirt/Sec/SecMain.c   | 4 +++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3af596..0e2a5785e8a4 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -48,6 +48,7 @@ [LibraryClasses]
   FdtLib
   MemoryAllocationLib
   HobLib
+  SerialPortLib
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid                # PPI ALWAYS_PRODUCED
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h
index 83a8058efe40..7c7650f0d298 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.h
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h
@@ -29,6 +29,7 @@
 #include <Library/PrePiLib.h>
 #include <Library/PlatformInitLib.h>
 #include <Library/PrePiHobListPointerLib.h>
+#include <Library/SerialPortLib.h>
 #include <Register/RiscV64/RiscVImpl.h>
 
 /**
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c
index adf73f2eb66c..b35c77774510 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.c
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   RISC-V SEC phase module for Qemu Virt.
 
-  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -57,6 +57,8 @@ SecStartup (
   UINT64                      StackBase;
   UINT32                      StackSize;
 
+  SerialPortInitialize ();
+
   //
   // Report Status Code to indicate entering SEC core
   //
-- 
2.25.1


  parent reply	other threads:[~2023-04-07 21:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-07 21:44 [PATCH v7 0/3] RISC-V SBI-backed SerialLib Andrei Warkentin
2023-04-07 21:44 ` [PATCH v7 1/3] MdePkg: BaseRiscVSbiLib: make more useful to consumers Andrei Warkentin
2023-04-07 21:44 ` [PATCH v7 2/3] MdePkg: add SBI-based SerialPortLib for RISC-V Andrei Warkentin
2023-04-12  7:15   ` Sunil V L
2023-04-18 23:31     ` [edk2-devel] " Andrei Warkentin
2023-04-07 21:44 ` Andrei Warkentin [this message]
2023-04-08  2:22   ` [edk2-devel] [PATCH v7 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Yao, Jiewen
2023-04-07 22:08 ` [edk2-devel] [PATCH v7 0/3] RISC-V SBI-backed SerialLib Michael D Kinney
2023-04-25 19:26   ` Andrei Warkentin
2023-04-26  6:44     ` Sunil V L
     [not found]   ` <1759444C5DA596CB.10313@groups.io>
2023-05-11 20:25     ` Andrei Warkentin
     [not found]     ` <175E309BD5A0B986.27409@groups.io>
2023-05-17  4:58       ` Andrei Warkentin
2023-05-17  5:06         ` Michael D Kinney
2023-05-17  5:26           ` Andrei Warkentin
2023-05-17 18:03             ` Michael D Kinney
2023-05-17 23:47               ` Michael D Kinney
2023-05-18  3:36                 ` Andrei Warkentin

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