From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.2109.1680903908685764456 for ; Fri, 07 Apr 2023 14:45:09 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=H/roST9D; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: andrei.warkentin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680903909; x=1712439909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+CYqfLx9Og59bLlZNot0oArgdfBHmHCbxfmYWsv5NWM=; b=H/roST9D7TMfCW9H2zlMNtNwMZRFrzgobQITCZfMgoKGsWYuLfNffDD8 MdG6eQ9zTIAvWDbEqutG9Hn8nDMTEEY+duJ+NPiJJv8NU6NNwomYfTpiI W9AAp+EkJYQFPA3Fgw+Nb6wV7lwLziK9OSoEGe0IGQfWvtY/WkIiWX9n5 KJuR1E1b8fwZKkc1h9f2tPZ/blqxOGbklcf2IyuT9friSg1nC39qYKXp+ 7HemQvmMyvtBk+2SuG57hxRG8h5IRprB1up9RGRWa7d0J/H9V85eFNMwu 8VWaavJa4KAC92fT3UX8egAxQY/PXh6WPJkWvJgJMAMwsGmYwv5e3C8zC w==; X-IronPort-AV: E=McAfee;i="6600,9927,10673"; a="343081075" X-IronPort-AV: E=Sophos;i="5.98,328,1673942400"; d="scan'208";a="343081075" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2023 14:44:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10673"; a="717964760" X-IronPort-AV: E=Sophos;i="5.98,328,1673942400"; d="scan'208";a="717964760" Received: from jsilva4x-mobl.amr.corp.intel.com (HELO awarkent-mobl1.amr.corp.intel.com) ([10.212.106.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2023 14:44:35 -0700 From: "Andrei Warkentin" To: devel@edk2.groups.io Cc: Andrei Warkentin , Daniel Schaefer , Sunil V L Subject: [PATCH v7 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Date: Fri, 7 Apr 2023 16:44:25 -0500 Message-Id: <20230407214425.4360-4-andrei.warkentin@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230407214425.4360-1-andrei.warkentin@intel.com> References: <20230407214425.4360-1-andrei.warkentin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Reviewed-by: Sunil V L Signed-off-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af596..0e2a5785e8a4 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ [LibraryClasses] FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe40..7c7650f0d298 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index adf73f2eb66c..b35c77774510 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // -- 2.25.1