From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:13 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=HfSC5o+M; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681289773; x=1712825773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xkhx+7/hkkL8jNidVkTReso6Kgk1rtk1iTKhZ4CmZac=; b=HfSC5o+MFkqfDisMjp8fRI1kfj04vHtlEMiui2MmogplEGUi1trrQqFA jWPO8SyUexz97EgSLBYKZJRL8gKQg2Or1vGZYLupX27yRqSDvRhmA6ywq p+Ax+Obl8pzrefeJLVht8DAAHUf0fAtFVvEdKXaW0fezb2LR3Kp1NM0Ip 9XTLoghHVCAHetmt/Pg/I0SPBoHQmUC7aodYkieCyArq1yDKk7yf8tEFL l6c0FbE7JsdjKn6gdoRBOk7Gq9E8C5FqHicyqLzStwhI9UiSkhpfZrgLW 5AqlY0hPBCde5rlrzPFA3Tyz7aGJinQgY4hj3bUqPHtPHiRn7M4cXiQyx w==; X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126799" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126799" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262100" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262100" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:07 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V2 5/8] UefiCpuPkg: Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h Date: Wed, 12 Apr 2023 16:53:40 +0800 Message-Id: <20230412085343.1077-6-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove extern for mSmmShadowStackSize in c files to simplify code. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 3 +-- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 3 +-- 5 files changed, 3 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c index 6c48a53f67..636dc8d92f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for Ia32 arch specific. -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -14,7 +14,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index baf827cf9d..1878252eac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -29,8 +29,6 @@ MM_COMPLETION mSmmStartupThisApToken; // UINT32 *mPackageFirstThreadIndex = NULL; -extern UINTN mSmmShadowStackSize; - /** Performs an atomic compare exchange operation to get semaphore. The compare exchange operation must be performed using diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index ba341cadc6..a155e09200 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -262,6 +262,7 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu; extern EFI_MM_MP_PROTOCOL mSmmMp; extern BOOLEAN m5LevelPagingNeeded; extern PAGING_MODE mPagingMode; +extern UINTN mSmmShadowStackSize; /// /// The mode of the CPU at the time an SMI occurs diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index a25a96f68c..25ced50955 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PAGE_TABLE_PAGES 8 #define ACC_MAX_BIT BIT3 -extern UINTN mSmmShadowStackSize; - LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); BOOLEAN m1GPageTableSupport = FALSE; BOOLEAN mCpuSmmRestrictedMemoryAccess; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index 00a284c369..c4f21e2155 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for x64 arch specific. -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -12,7 +12,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; -- 2.39.1.windows.1