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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id g20-20020a170902869400b001a681d123a0sm3329760plo.297.2023.04.14.11.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 11:58:33 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, Tuan Phan Subject: [PATCH v2 0/6] RISC-V MMU support Date: Fri, 14 Apr 2023 11:58:09 -0700 Message-Id: <20230414185815.2994-1-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (6): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1