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From: "Zhiguang Liu" <zhiguang.liu@intel.com>
To: devel@edk2.groups.io
Cc: Zhiguang Liu <zhiguang.liu@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>,
	Ray Ni <ray.ni@intel.com>
Subject: [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False
Date: Tue, 25 Apr 2023 14:37:09 +0800	[thread overview]
Message-ID: <20230425063709.1951-1-zhiguang.liu@intel.com> (raw)

In BoardX58Ich10 platform, MSR 0x1f2 (ia32_smrr_physbase) and MSR 0x1f3
(ia32_smrr_physmask) are both unimplemented. So set the PcdSmrrEnable
as disable to avoid access SMRR

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 .../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index 472318cc44..732d95e44f 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
@@ -39,6 +39,7 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
   gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|FALSE
+  gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|FALSE
 
   ######################################
   # Platform Configuration
-- 
2.31.1.windows.1


             reply	other threads:[~2023-04-25  6:38 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-25  6:37 Zhiguang Liu [this message]
2023-04-25  6:59 ` [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False Ni, Ray

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