* [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False
@ 2023-04-25 6:37 Zhiguang Liu
2023-04-25 6:59 ` Ni, Ray
0 siblings, 1 reply; 2+ messages in thread
From: Zhiguang Liu @ 2023-04-25 6:37 UTC (permalink / raw)
To: devel; +Cc: Zhiguang Liu, Nate DeSimone, Ray Ni
In BoardX58Ich10 platform, MSR 0x1f2 (ia32_smrr_physbase) and MSR 0x1f3
(ia32_smrr_physmask) are both unimplemented. So set the PcdSmrrEnable
as disable to avoid access SMRR
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index 472318cc44..732d95e44f 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
@@ -39,6 +39,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|FALSE
######################################
# Platform Configuration
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False
2023-04-25 6:37 [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False Zhiguang Liu
@ 2023-04-25 6:59 ` Ni, Ray
0 siblings, 0 replies; 2+ messages in thread
From: Ni, Ray @ 2023-04-25 6:59 UTC (permalink / raw)
To: Liu, Zhiguang, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L
Reviewed-by: Ray Ni <ray.ni@intel.com>
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: Tuesday, April 25, 2023 2:37 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Ni, Ray <ray.ni@intel.com>
> Subject: [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as
> False
>
> In BoardX58Ich10 platform, MSR 0x1f2 (ia32_smrr_physbase) and MSR 0x1f3
> (ia32_smrr_physmask) are both unimplemented. So set the PcdSmrrEnable
> as disable to avoid access SMRR
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> ---
> .../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
> c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
> c
> index 472318cc44..732d95e44f 100644
> ---
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
> c
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
> c
> @@ -39,6 +39,7 @@
> gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|FALSE
> + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|FALSE
>
> ######################################
> # Platform Configuration
> --
> 2.31.1.windows.1
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-04-25 7:00 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-25 6:37 [PATCH] SimicsOpenBoardPkg: BoardX58Ich10 set PcdSmrrEnable as False Zhiguang Liu
2023-04-25 6:59 ` Ni, Ray
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox