From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:18 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ApIcBkGc; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682406198; x=1713942198; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jrx6RXdoXFLMZ0JJvWtZxj3eMFQERBeM1dRujC/80jU=; b=ApIcBkGcmi2iCqlM/WKiS3rk/BeLIW6cu1yYHLviqrS+QVTeVrLtf9C6 r5ftlXNa9jviXyL/291zRq2e7Gsjg8BvC2k5BJmFOE7IdSEbRmeW8hPhI Ok7jMZ53xWcLzxZHuHZ7JJ9g/WVEU8mwHMUcj3tgJCVFBvtx1Z13NRI9H Dy/J24O/8n7BkySNmDBrZS2FohJehUMIGi0PUWYMlMSi9b1X65yuO/8We lDdSzYMDSmtJuwmDqpyLdHVAsHt/UF0BYCuls58LiyZle7G5LXN3CPcd/ vFwb5n8uNYjkWObZ0bo0XCG54ZIWFFUnrglgskINjCqrtw2JP03jzq5Rd g==; X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623053" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623053" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781589" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781589" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:17 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [PATCH 2/5] SimicsOpenBoardPkg: Move AcpiVariableGuid hob to MemDetect Date: Tue, 25 Apr 2023 15:03:01 +0800 Message-Id: <20230425070304.2120-3-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, MemDetect create gEfiSmmSmramMemoryGuid Hob containing one descriptor, which should be updated later, when AcpiVariableGuid hob use some buffer from SmRam. However, the Hob doesn't get updated, and this is a bug. Move the logic creating AcpiVariableGuid hob from PEIM SmmAccessPei.inf to MemDetect, so that in the same file, it has both knowleage about the smmram and the acpi data structure. So it can create the gEfiSmmSmramMemoryGuid Hob containing two descriptors. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu --- .../SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 36 +++++++++++-------- .../SimicsPei/SimicsPei.inf | 1 + .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.c | 8 ----- .../Smm/Access/SmmAccessPei.inf | 3 -- 4 files changed, 22 insertions(+), 26 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index d80ac1d213..13ee415f40 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -391,11 +391,10 @@ QemuInitializeRam ( UINT64 LowerMemorySize; UINT64 UpperMemorySize; UINTN BufferSize; - UINT8 SmramIndex; UINT8 SmramRanges; EFI_PEI_HOB_POINTERS Hob; EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - UINT8 Index; + VOID *GuidHob; DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__)); @@ -418,8 +417,8 @@ QemuInitializeRam ( AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); - BufferSize = sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); - SmramRanges = 1; + SmramRanges = 2; + BufferSize = sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (SmramRanges - 1) * sizeof(EFI_SMRAM_DESCRIPTOR); Hob.Raw = BuildGuidHob( &gEfiSmmSmramMemoryGuid, @@ -430,18 +429,25 @@ QemuInitializeRam ( SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw); SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges; - SmramIndex = 0; - for (Index = 0; Index < SmramRanges; Index++) { - // - // This is an SMRAM range, create an SMRAM descriptor - // - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = LowerMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = LowerMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; - SmramIndex++; - } + // + // Create first SMRAM descriptor, which contains data structures used in S3 resume. + // One page is enough for the data structure + // + SmramHobDescriptorBlock->Descriptor[0].PhysicalStart = LowerMemorySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[0].CpuStart = LowerMemorySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[0].PhysicalSize = EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[0].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE | EFI_ALLOCATED; + GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid, sizeof(EFI_SMRAM_DESCRIPTOR)); + ASSERT (GuidHob != NULL); + CopyMem (GuidHob, &SmramHobDescriptorBlock->Descriptor[0], sizeof(EFI_SMRAM_DESCRIPTOR)); + // + // Create second SMRAM descriptor, which is free and will be used by SMM foundation. + // + SmramHobDescriptorBlock->Descriptor[1].PhysicalStart = SmramHobDescriptorBlock->Descriptor[0].PhysicalStart + EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].CpuStart = SmramHobDescriptorBlock->Descriptor[0].CpuStart + EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].PhysicalSize = TsegSize - EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf index 710fa680be..618ad4075f 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf @@ -40,6 +40,7 @@ [Guids] gEfiMemoryTypeInformationGuid gEfiSmmSmramMemoryGuid ## CONSUMES + gEfiAcpiVariableGuid [LibraryClasses] BaseLib diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c index c54026b4d1..d489cc7513 100644 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c +++ b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c @@ -241,7 +241,6 @@ SmmAccessPeiEntryPoint ( EFI_STATUS Status; UINTN SmramMapSize; EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount]; - VOID *GuidHob; // // This module should only be included if SMRAM support is required. @@ -322,13 +321,6 @@ SmmAccessPeiEntryPoint ( } DEBUG_CODE_END (); - GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid, sizeof SmramMap[DescIdxSmmS3ResumeState]); - if (GuidHob == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState], sizeof SmramMap[DescIdxSmmS3ResumeState]); - // // We're done. The next step should succeed, but even if it fails, we can't // roll back the above BuildGuidHob() allocation, because PEI doesn't support diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf index 2b6b14f437..3c71e64fe9 100644 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf +++ b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf @@ -38,9 +38,6 @@ SimicsX58SktPkg/SktPkg.dec SimicsIch10Pkg/Ich10Pkg.dec -[Guids] - gEfiAcpiVariableGuid - [LibraryClasses] BaseLib BaseMemoryLib -- 2.31.1.windows.1