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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT003.mail.protection.outlook.com (100.127.142.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6340.20 via Frontend Transport; Tue, 25 Apr 2023 16:04:34 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Tue, 25 Apr 2023 16:04:33 +0000 Received: from E114225.Arm.com (10.1.196.36) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Tue, 25 Apr 2023 16:04:33 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , , , Subject: [RFC PATCH v1 04/30] ArmPkg: Extend number of parameter registers in SMC call Date: Tue, 25 Apr 2023 17:04:02 +0100 Message-ID: <20230425160428.27980-5-sami.mujawar@arm.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230425160428.27980-1-sami.mujawar@arm.com> References: <20230425160428.27980-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT003:EE_|AS8PR08MB9672:EE_|DBAEUR03FT023:EE_|AS2PR08MB9414:EE_ X-MS-Office365-Filtering-Correlation-Id: 7744e3d2-bb1b-4e9d-50e0-08db45a727f2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2023 16:07:23.5103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7744e3d2-bb1b-4e9d-50e0-08db45a727f2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9414 Content-Type: text/plain The Realm Service Interface (RSI) commands use registers between X1-X10 as parameters and between X0-X8 as return values for SMC calls. According to the SMCCC Section 2.6 SMC32/HVC32 argument passing When an SMC32/HVC32 call is made from AArch32: - Arguments are passed in registers R1-R7. - Results are returned in R0-R7. When an SMC32/HVC32 call is made from AArch64: - Arguments are passed in registers W1-W7. - Results are returned in W0-W7. According to SMCCC Section 2.7 SMC64/HVC64 argument passing When an SMC64/HVC64 call is made from AArch64: - Arguments are passed in registers X1-X17. - Results are returned in X0-X17. This means SMC calls can take up to 7/17 arguments and return up to 7/17 return values. However, for the current use-case(s): - SMC32/HVC32 calls made from AArch32/AArch64 require up to 7 arguments and 4 return values. - SMC64/HVC64 calls made from AArch64 require up to 10 arguments and 9 return values. Therefore, for SMC32/HVC32 calls made from AArch32/AArch64 there is no update required. However, for AMC64/HVC64 calls made from AArch64, extend the ArmCallSmc () to use registers X1-X11 as parameters and return values for SMC call. Signed-off-by: Sami Mujawar --- ArmPkg/Include/Library/ArmSmcLib.h | 50 ++++++++++++++++++-- ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S | 22 ++++++--- 2 files changed, 62 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Include/Library/ArmSmcLib.h b/ArmPkg/Include/Library/ArmSmcLib.h index beef0175c35ce86aac9e465f9062bf8052b08dfb..e80b74671a6424723323bab95917fb3909771759 100644 --- a/ArmPkg/Include/Library/ArmSmcLib.h +++ b/ArmPkg/Include/Library/ArmSmcLib.h @@ -1,10 +1,13 @@ /** @file * * Copyright (c) 2021, NUVIA Inc. All rights reserved.
-* Copyright (c) 2012-2014, ARM Limited. All rights reserved. +* Copyright (c) 2012-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * +* @par Reference(s): +* - SMC Calling Convention (SMCCC), ARM DEN 0028E, EAC0, 1.4 +* (https://developer.arm.com/documentation/den0028/e/) **/ #ifndef ARM_SMC_LIB_H_ @@ -13,6 +16,18 @@ /** * The size of the SMC arguments are different between AArch64 and AArch32. * The native size is used for the arguments. + * According to the SMCCC Section 2.6 SMC32/HVC32 argument passing + * When an SMC32/HVC32 call is made from AArch32: + * - Arguments are passed in registers R1-R7. + * - Results are returned in R0-R7. + * When an SMC32/HVC32 call is made from AArch64: + * - Arguments are passed in registers W1-W7. + * - Results are returned in W0-W7. + * + * According to SMCCC Section 2.7 SMC64/HVC64 argument passing + * When an SMC64/HVC64 call is made from AArch64: + * - Arguments are passed in registers X1-X17. + * - Results are returned in X0-X17. */ typedef struct { UINTN Arg0; @@ -23,13 +38,42 @@ typedef struct { UINTN Arg5; UINTN Arg6; UINTN Arg7; + #ifdef MDE_CPU_AARCH64 + UINTN Arg8; + UINTN Arg9; + UINTN Arg10; + UINTN Arg11; + #endif } ARM_SMC_ARGS; /** Trigger an SMC call - SMC calls can take up to 7 arguments and return up to 4 return values. - Therefore, the 4 first fields in the ARM_SMC_ARGS structure are used + According to the SMCCC Section 2.6 SMC32/HVC32 argument passing + When an SMC32/HVC32 call is made from AArch32: + - Arguments are passed in registers R1-R7. + - Results are returned in R0-R7. + When an SMC32/HVC32 call is made from AArch64: + - Arguments are passed in registers W1-W7. + - Results are returned in W0-W7. + + According to SMCCC Section 2.7 SMC64/HVC64 argument passing + When an SMC64/HVC64 call is made from AArch64: + - Arguments are passed in registers X1-X17. + - Results are returned in X0-X17. + + This means SMC calls can take up to 7/17 arguments and return up + to 7/17 return values. + + However, the current use-case: + - For SMC32/HVC32 calls made from AArch32/AArch64 up to 7 arguments + and 4 return values are required. Therefore, limit the maximum + arguments to 7 and return values to 4. + - For AMC64/HVC64 calls made from AArch64 up to 11 arguments and + return values are required. Therefore, limit the maximum arguments + and return values to 11. + + The fields in the ARM_SMC_ARGS structure are used for both input and output values. **/ diff --git a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S index 4a8c2a8f59eab3e5b66dda2515d5bbced131af13..299d612dc5e1ebfeaf69a356b400c511905d72fe 100644 --- a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S +++ b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S @@ -1,8 +1,11 @@ // -// Copyright (c) 2012-2014, ARM Limited. All rights reserved. +// Copyright (c) 2012-2023, Arm Limited. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // +// @par Reference(s): +// - SMC Calling Convention (SMCCC), ARM DEN 0028E, EAC0, 1.4 +// (https://developer.arm.com/documentation/den0028/e/) // #include @@ -12,6 +15,8 @@ ASM_FUNC(ArmCallSmc) str x0, [sp, #-16]! // Load the SMC arguments values into the appropriate registers + ldp x10, x11, [x0, #80] + ldp x8, x9, [x0, #64] ldp x6, x7, [x0, #48] ldp x4, x5, [x0, #32] ldp x2, x3, [x0, #16] @@ -19,14 +24,17 @@ ASM_FUNC(ArmCallSmc) smc #0 - // Pop the ARM_SMC_ARGS structure address from the stack into x9 - ldr x9, [sp], #16 + // Pop the ARM_SMC_ARGS structure address from the stack into x13 + ldr x13, [sp], #16 // Store the SMC returned values into the ARM_SMC_ARGS structure. - // A SMC call can return up to 4 values - we do not need to store back x4-x7. - stp x2, x3, [x9, #16] - stp x0, x1, [x9, #0] + stp x10, x11, [x13, #80] + stp x8, x9, [x13, #64] + stp x6, x7, [x13, #48] + stp x4, x5, [x13, #32] + stp x2, x3, [x13, #16] + stp x0, x1, [x13, #0] - mov x0, x9 + mov x0, x13 ret -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'