From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.1740.1682489774480026272 for ; Tue, 25 Apr 2023 23:16:14 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=NiYlWGjy; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682489774; x=1714025774; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8DgCTV2U0jeMlf/TSj5pvVUxy1SnkQIYEzzodtJ2Vro=; b=NiYlWGjy3SlmtlHNrIAScDj+1nWNLD0KC2K8kk2Rlewj7sknaJnP/IE+ axGP1qvvFhsqwFv5EtbdHieYAnVfypfxfTiOW/ToEBehq/AHTcoZTLL1O CCyAlqW9dbol9y/Ak+PIvZwwqQAzIArhb5+G8qgr16mauCRDwGkzz02xb W6+xgOlxeOyF/EoJ/w+d1++t4VbgckPmoKmXZ8Tcuz2pMF90z2cz60277 JDBLx9KqVQlcHH6Ff1iM3CHptjTaSm8ZwxMvLcVjZIsFZR3XfVyvmTTUj zOk6Fjk6dbNIr0EC1NWsAXJzrrbEO4WUXVd8jA7wmrIAroGhxDMwfZsqx g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="331235150" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="331235150" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 23:16:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="644125184" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="644125184" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 23:16:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [PATCH v2 1/5] SimicsOpenBoardPkg: Build gEfiSmmSmramMemoryGuid Hob in S3 path Date: Wed, 26 Apr 2023 14:15:45 +0800 Message-Id: <20230426061549.1254-2-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230426061549.1254-1-zhiguang.liu@intel.com> References: <20230426061549.1254-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit gEfiSmmSmramMemoryGuid Hob is needed for SmmRelocation feature even for S3 path. So in MemDetect.c, remove specical code path for S3 about creating gEfiSmmSmramMemoryGuid Hob and adding some memory descriptor, which does no harm in S3 path. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu --- .../SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 119 ++++++++---------- 1 file changed, 53 insertions(+), 66 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index 127afffc00..b79e8eb73a 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -1,7 +1,7 @@ /** @file Memory Detection for Virtual Machines. - Copyright (c) 2006 - 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2023 Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -405,79 +405,66 @@ QemuInitializeRam ( LowerMemorySize = GetSystemMemorySizeBelow4gb (); UpperMemorySize = GetSystemMemorySizeAbove4gb (); - if (mBootMode == BOOT_ON_S3_RESUME) { - // - // Create the following memory HOB as an exception on the S3 boot path. - // - // Normally we'd create memory HOBs only on the normal boot path. However, - // CpuMpPei specifically needs such a low-memory HOB on the S3 path as - // well, for "borrowing" a subset of it temporarily, for the AP startup - // vector. - // - // CpuMpPei saves the original contents of the borrowed area in permanent - // PEI RAM, in a backup buffer allocated with the normal PEI services. - // CpuMpPei restores the original contents ("returns" the borrowed area) at - // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before - // transferring control to the OS's wakeup vector in the FACS. - // - // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to - // restore the original contents. Furthermore, we expect all such PEIMs - // (CpuMpPei included) to claim the borrowed areas by producing memory - // allocation HOBs, and to honor preexistent memory allocation HOBs when - // looking for an area to borrow. - // - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - } else { - // - // Create memory HOBs - // - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + // + // CpuMpPei saves the original contents of the borrowed area in permanent + // PEI RAM, in a backup buffer allocated with the normal PEI services. + // CpuMpPei restores the original contents ("returns" the borrowed area) at + // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before + // transferring control to the OS's wakeup vector in the FACS. + // + // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to + // restore the original contents. Furthermore, we expect all such PEIMs + // (CpuMpPei included) to claim the borrowed areas by producing memory + // allocation HOBs, and to honor preexistent memory allocation HOBs when + // looking for an area to borrow. + // + AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - if (FeaturePcdGet (PcdSmmSmramRequire)) { - UINT32 TsegSize; + if (FeaturePcdGet (PcdSmmSmramRequire)) { + UINT32 TsegSize; - TsegSize = mX58TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, - TRUE); + TsegSize = mX58TsegMbytes * SIZE_1MB; + AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, + TRUE); - BufferSize = sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); - SmramRanges = 1; + BufferSize = sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); + SmramRanges = 1; - Hob.Raw = BuildGuidHob( - &gEfiSmmSmramMemoryGuid, - BufferSize - ); - ASSERT(Hob.Raw); - - SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw); - SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges; - - SmramIndex = 0; - for (Index = 0; Index < SmramRanges; Index++) { - // - // This is an SMRAM range, create an SMRAM descriptor - // - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = LowerMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = LowerMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; - SmramIndex++; - } + Hob.Raw = BuildGuidHob( + &gEfiSmmSmramMemoryGuid, + BufferSize + ); + ASSERT(Hob.Raw); - } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); - } + SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw); + SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges; - // - // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM - // entries. Otherwise, create a single memory HOB with the flat >=4GB - // memory size read from the CMOS. - // - if (UpperMemorySize != 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + SmramIndex = 0; + for (Index = 0; Index < SmramRanges; Index++) { + // + // This is an SMRAM range, create an SMRAM descriptor + // + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = LowerMemorySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = LowerMemorySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = TsegSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE; + SmramIndex++; } + + } else { + AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } + + // + // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM + // entries. Otherwise, create a single memory HOB with the flat >=4GB + // memory size read from the CMOS. + // + if (UpperMemorySize != 0) { + AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + } + } /** -- 2.31.1.windows.1