* [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
@ 2023-04-26 8:13 Zhiguang Liu
2023-04-26 8:13 ` [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table " Zhiguang Liu
2023-04-26 8:25 ` [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table " Zhiguang Liu
0 siblings, 2 replies; 5+ messages in thread
From: Zhiguang Liu @ 2023-04-26 8:13 UTC (permalink / raw)
To: devel
Cc: Zhiguang Liu, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West
In ResetVector, if create page table, its highest address is fixed
because after page table, code layout is fixed(4K for normal code,
and another 4K only contains reset vector code).
Today's implementation organizes the page table as following if 1G
page table is used:
4G-16K: PML4 page (PML4[0] points to 4G-12K)
4G-12K: PDP page
CR3 is set to 4G-16K
When 2M page table is used, the layout is as following:
4G-32K: PML4 page (PML4[0] points to 4G-28K)
4G-28K: PDP page (PDP entries point to PD pages)
4G-24K: PD page mapping 0-1G
4G-20K: PD page mapping 1-2G
4G-16K: PD page mapping 2-3G
4G-12K: PD page mapping 3-4G
CR3 is set to 4G-32K
CR3 doesn't point to a fixed location which is a bit hard to debug at
runtime.
The new page table layout will always put PML4 in highest address
When 1G page table is used, the layout is as following:
4G-16K: PDP page
4G-12K: PML4 page (PML4[0] points to 4G-16K)
When 2M page table is used, the layout is as following:
4G-32K: PD page mapping 0-1G
4G-28K: PD page mapping 1-2G
4G-24K: PD page mapping 2-3G
4G-20K: PD page mapping 3-4G
4G-16K: PDP page (PDP entries point to PD pages)
4G-12K: PML4 page (PML4[0] points to 4G-16K)
CR3 is always set to 4G-16K
So, this patch can improve debuggability by make sure the init
CR3 pointting to a fixed address(4G-12K).
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 3 +-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 +
.../ResetVector/Vtf0/X64/PageTables1G.asm | 29 ++++++-------
.../ResetVector/Vtf0/X64/PageTables2M.asm | 43 +++++++++----------
4 files changed, 37 insertions(+), 39 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index 87a4125d4b..717e380892 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -16,8 +16,9 @@ SetCr3ForPageTables64:
;
; These pages are built into the ROM image in X64/PageTables.asm
+ ; Highest level PageTable is at the highest address
;
- mov eax, ADDR_OF(TopLevelPageDirectory)
+ mov eax, ADDR_OF(PML4Table)
mov cr3, eax
OneTimeCallRet SetCr3ForPageTables64
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index bdea1fb875..4b972a90a5 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -44,6 +44,7 @@
%include "X64/PageTables2M.asm"
%endif
%endif
+EndOfPageTables:
%ifdef DEBUG_PORT80
%include "Port80Debug.asm"
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
index 19bd3d5a92..a0f477b5b0 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
;
-; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Linear-Address Translation to a 1-GByte Page
;
@@ -22,32 +22,29 @@ BITS 64
PAGE_PRESENT + \
PAGE_SIZE)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
PAGE_PDP_ATTR)
%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
ALIGN 16
-
-TopLevelPageDirectory:
-
- ;
- ; Top level Page Directory Pointers (1 * 512GB entry)
- ;
- DQ PDP(0x1000)
-
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+StartOfPageTables:
;
- ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ; Page-directory pointer table Pointers (512 * 1GB entries => 512GB)
+ ; Contains one page
;
%assign i 0
%rep 512
DQ PDP_1G(i)
%assign i i+1
%endrep
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
-EndOfPageTables:
+PML4Table:
+ ;
+ ; PML4 table Pointers (1 * 512GB entry)
+ ;
+ DQ PDP(0)
+
+ TIMES 0x2000-PGTBLS_OFFSET($) DB 0
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
index b97df384ac..0200825876 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
;
-; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -21,40 +21,39 @@ BITS 64
PAGE_READ_WRITE + \
PAGE_PRESENT)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
PAGE_PDP_ATTR)
%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
-TopLevelPageDirectory:
+ALIGN 16
+StartOfPageTables:
;
- ; Top level Page Directory Pointers (1 * 512GB entry)
+ ; Page Table Entries (2048 * 2MB entries => 4GB)
+ ; Contains 4 pages
;
- DQ PDP(0x1000)
-
+%assign i 0
+%rep 0x800
+ DQ PTE_2MB(i)
+ %assign i i+1
+%endrep
;
- ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
+ ; Page-directory pointer table Pointers (4 * 1GB entries => 4GB)
+ ; here is at offset 0x4000 from StartOfPageTables
;
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
-
+ DQ PDP(0)
+ DQ PDP(0x1000)
DQ PDP(0x2000)
DQ PDP(0x3000)
- DQ PDP(0x4000)
- DQ PDP(0x5000)
+ TIMES 0x5000-PGTBLS_OFFSET($) DB 0
+PML4Table:
;
- ; Page Table Entries (2048 * 2MB entries => 4GB)
+ ; PML4 table Pointers (1 * 512GB entry)
;
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
-
-%assign i 0
-%rep 0x800
- DQ PTE_2MB(i)
- %assign i i+1
-%endrep
+ DQ PDP(0x4000)
-EndOfPageTables:
+ TIMES 0x6000-PGTBLS_OFFSET($) DB 0
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table in ResetVector
2023-04-26 8:13 [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
@ 2023-04-26 8:13 ` Zhiguang Liu
2023-04-26 9:07 ` Ni, Ray
2023-04-26 8:25 ` [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table " Zhiguang Liu
1 sibling, 1 reply; 5+ messages in thread
From: Zhiguang Liu @ 2023-04-26 8:13 UTC (permalink / raw)
To: devel
Cc: Zhiguang Liu, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
paging is not created, and 4level paging is at (4G-12K) and be used.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 24 ++++++++++++++++--
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 25 -------------------
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 ++-
.../ResetVector/Vtf0/X64/PageTables5L.asm | 20 +++++++++++++++
4 files changed, 45 insertions(+), 28 deletions(-)
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
index 6891397c2a..0b4a21061b 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
@@ -2,7 +2,7 @@
; @file
; Transition from 32 bit flat protected mode into 64 bit flat protected mode
;
-; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -13,8 +13,28 @@ BITS 32
; Modified: EAX
;
Transition32FlatTo64Flat:
+%ifdef USE_5_LEVEL_PAGE_TABLE
+ mov eax, 0
+ cpuid
+ cmp eax, 07h ; check if basic CPUID leaf contains leaf 07
+ jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
+ mov eax, 07h ; check cpuid leaf 7, subleaf 0
+ mov ecx, 0
+ cpuid
+ bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1.
+ jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
+ mov eax, ADDR_OF(PML5Table)
+ mov cr3, eax
+ mov eax, cr4
+ bts eax, 12 ; Set LA57=1.
+ mov cr4, eax
+ jmp CR3ProgramDone
+NotSupport5LevelPaging:
+%endif
- OneTimeCall SetCr3ForPageTables64
+ mov eax, ADDR_OF(PML4Table)
+ mov cr3, eax
+CR3ProgramDone:
mov eax, cr4
bts eax, 5 ; enable PAE
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
deleted file mode 100644
index 717e380892..0000000000
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-;------------------------------------------------------------------------------
-; @file
-; Sets the CR3 register for 64-bit paging
-;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-;------------------------------------------------------------------------------
-
-BITS 32
-
-;
-; Modified: EAX
-;
-SetCr3ForPageTables64:
-
- ;
- ; These pages are built into the ROM image in X64/PageTables.asm
- ; Highest level PageTable is at the highest address
- ;
- mov eax, ADDR_OF(PML4Table)
- mov cr3, eax
-
- OneTimeCallRet SetCr3ForPageTables64
-
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 4b972a90a5..ececa244e3 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -43,6 +43,9 @@
%else
%include "X64/PageTables2M.asm"
%endif
+%ifdef USE_5_LEVEL_PAGE_TABLE
+ %include "X64/PageTables5L.asm"
+%endif
%endif
EndOfPageTables:
@@ -59,7 +62,6 @@ EndOfPageTables:
%ifdef ARCH_X64
%include "Ia32/Flat32ToFlat64.asm"
-%include "Ia32/PageTables64.asm"
%endif
%include "Ia16/Real16ToFlat32.asm"
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
new file mode 100644
index 0000000000..62c9be047a
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
@@ -0,0 +1,20 @@
+;------------------------------------------------------------------------------
+; @file
+; PML5 page table creation.
+;
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+PML5Table:
+ ;
+ ; PML5 table Pointers
+ ; Assume page table is create from bottom to top, and only one PML4 table there.
+ ;
+ DQ (ADDR_OF($) - 0x1000 + PAGE_PDP_ATTR)
+
+ ;
+ ; Only first PML5 entry(first 8 bytes) pointting to a PML4 table. Others are zero
+ ;
+ TIMES (0x1000 - 0x8) DB 0
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
2023-04-26 8:13 [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
2023-04-26 8:13 ` [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table " Zhiguang Liu
@ 2023-04-26 8:25 ` Zhiguang Liu
2023-04-26 8:58 ` Ni, Ray
1 sibling, 1 reply; 5+ messages in thread
From: Zhiguang Liu @ 2023-04-26 8:25 UTC (permalink / raw)
To: devel@edk2.groups.io
Cc: Dong, Eric, Ni, Ray, Kumar, Rahul R, Gerd Hoffmann, De, Debkumar,
West, Catharine
Correct a typo in commit message inline.
Thanks
Zhiguang
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: Wednesday, April 26, 2023 4:13 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; De,
> Debkumar <debkumar.de@intel.com>; West, Catharine
> <catharine.west@intel.com>
> Subject: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in
> ResetVector
>
> In ResetVector, if create page table, its highest address is fixed because after
> page table, code layout is fixed(4K for normal code, and another 4K only
> contains reset vector code).
> Today's implementation organizes the page table as following if 1G page
> table is used:
> 4G-16K: PML4 page (PML4[0] points to 4G-12K)
> 4G-12K: PDP page
> CR3 is set to 4G-16K
> When 2M page table is used, the layout is as following:
> 4G-32K: PML4 page (PML4[0] points to 4G-28K)
> 4G-28K: PDP page (PDP entries point to PD pages)
> 4G-24K: PD page mapping 0-1G
> 4G-20K: PD page mapping 1-2G
> 4G-16K: PD page mapping 2-3G
> 4G-12K: PD page mapping 3-4G
> CR3 is set to 4G-32K
> CR3 doesn't point to a fixed location which is a bit hard to debug at runtime.
>
> The new page table layout will always put PML4 in highest address When 1G
> page table is used, the layout is as following:
> 4G-16K: PDP page
> 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used,
> the layout is as following:
> 4G-32K: PD page mapping 0-1G
> 4G-28K: PD page mapping 1-2G
> 4G-24K: PD page mapping 2-3G
> 4G-20K: PD page mapping 3-4G
> 4G-16K: PDP page (PDP entries point to PD pages)
> 4G-12K: PML4 page (PML4[0] points to 4G-16K)
> CR3 is always set to 4G-16K
Zhiguang: This should be "CR3 is always set to 4G-12K"
> So, this patch can improve debuggability by make sure the init
> CR3 pointting to a fixed address(4G-12K).
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Debkumar De <debkumar.de@intel.com>
> Cc: Catharine West <catharine.west@intel.com>
> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> ---
> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 3 +-
> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 +
> .../ResetVector/Vtf0/X64/PageTables1G.asm | 29 ++++++-------
> .../ResetVector/Vtf0/X64/PageTables2M.asm | 43 +++++++++----------
> 4 files changed, 37 insertions(+), 39 deletions(-)
>
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> index 87a4125d4b..717e380892 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> @@ -16,8 +16,9 @@ SetCr3ForPageTables64:
>
> ;
> ; These pages are built into the ROM image in X64/PageTables.asm
> + ; Highest level PageTable is at the highest address
> ;
> - mov eax, ADDR_OF(TopLevelPageDirectory)
> + mov eax, ADDR_OF(PML4Table)
> mov cr3, eax
>
> OneTimeCallRet SetCr3ForPageTables64 diff --git
> a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> index bdea1fb875..4b972a90a5 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> @@ -44,6 +44,7 @@
> %include "X64/PageTables2M.asm"
> %endif
> %endif
> +EndOfPageTables:
>
> %ifdef DEBUG_PORT80
> %include "Port80Debug.asm"
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> index 19bd3d5a92..a0f477b5b0 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> @@ -2,7 +2,7 @@
> ; @file
> ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000
> (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation
> to a 1-GByte Page ;
> @@ -22,32 +22,29 @@ BITS 64
> PAGE_PRESENT + \
> PAGE_SIZE)
>
> -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define
> PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
> +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
>
> -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
> PAGE_PDP_ATTR)
>
> %define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
>
> ALIGN 16
> -
> -TopLevelPageDirectory:
> -
> - ;
> - ; Top level Page Directory Pointers (1 * 512GB entry)
> - ;
> - DQ PDP(0x1000)
> -
> - TIMES 0x1000-PGTBLS_OFFSET($) DB 0
> +StartOfPageTables:
> ;
> - ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
> + ; Page-directory pointer table Pointers (512 * 1GB entries => 512GB)
> + ; Contains one page
> ;
> %assign i 0
> %rep 512
> DQ PDP_1G(i)
> %assign i i+1
> %endrep
> - TIMES 0x2000-PGTBLS_OFFSET($) DB 0
>
> -EndOfPageTables:
> +PML4Table:
> + ;
> + ; PML4 table Pointers (1 * 512GB entry)
> + ;
> + DQ PDP(0)
> +
> + TIMES 0x2000-PGTBLS_OFFSET($) DB 0
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> index b97df384ac..0200825876 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> @@ -2,7 +2,7 @@
> ; @file
> ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ;
> -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights
> +reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;
> ;------------------------------------------------------------------------------
> @@ -21,40 +21,39 @@ BITS 64
> PAGE_READ_WRITE + \
> PAGE_PRESENT)
>
> -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define
> PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
> +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
>
> -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
> PAGE_PDP_ATTR)
> %define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
>
> -TopLevelPageDirectory:
> +ALIGN 16
> +StartOfPageTables:
>
> ;
> - ; Top level Page Directory Pointers (1 * 512GB entry)
> + ; Page Table Entries (2048 * 2MB entries => 4GB)
> + ; Contains 4 pages
> ;
> - DQ PDP(0x1000)
> -
> +%assign i 0
> +%rep 0x800
> + DQ PTE_2MB(i)
> + %assign i i+1
> +%endrep
>
> ;
> - ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
> + ; Page-directory pointer table Pointers (4 * 1GB entries => 4GB)
> + ; here is at offset 0x4000 from StartOfPageTables
> ;
> - TIMES 0x1000-PGTBLS_OFFSET($) DB 0
> -
> + DQ PDP(0)
> + DQ PDP(0x1000)
> DQ PDP(0x2000)
> DQ PDP(0x3000)
> - DQ PDP(0x4000)
> - DQ PDP(0x5000)
> + TIMES 0x5000-PGTBLS_OFFSET($) DB 0
>
> +PML4Table:
> ;
> - ; Page Table Entries (2048 * 2MB entries => 4GB)
> + ; PML4 table Pointers (1 * 512GB entry)
> ;
> - TIMES 0x2000-PGTBLS_OFFSET($) DB 0
> -
> -%assign i 0
> -%rep 0x800
> - DQ PTE_2MB(i)
> - %assign i i+1
> -%endrep
> + DQ PDP(0x4000)
>
> -EndOfPageTables:
> + TIMES 0x6000-PGTBLS_OFFSET($) DB 0
> --
> 2.31.1.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
2023-04-26 8:25 ` [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table " Zhiguang Liu
@ 2023-04-26 8:58 ` Ni, Ray
0 siblings, 0 replies; 5+ messages in thread
From: Ni, Ray @ 2023-04-26 8:58 UTC (permalink / raw)
To: Liu, Zhiguang, devel@edk2.groups.io
Cc: Dong, Eric, Kumar, Rahul R, Gerd Hoffmann, De, Debkumar,
West, Catharine
1. Can you please update the comments to use proper name for each level of paging entry?
Page-directory pointer table Pointers -> Page Directory Pointer Table
PML4 table pointers -> PML4
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: Wednesday, April 26, 2023 4:25 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar,
> Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>;
> De, Debkumar <debkumar.de@intel.com>; West, Catharine
> <catharine.west@intel.com>
> Subject: RE: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in
> ResetVector
>
> Correct a typo in commit message inline.
>
> Thanks
> Zhiguang
>
> > -----Original Message-----
> > From: Liu, Zhiguang <zhiguang.liu@intel.com>
> > Sent: Wednesday, April 26, 2023 4:13 PM
> > To: devel@edk2.groups.io
> > Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric
> > <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> > <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; De,
> > Debkumar <debkumar.de@intel.com>; West, Catharine
> > <catharine.west@intel.com>
> > Subject: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in
> > ResetVector
> >
> > In ResetVector, if create page table, its highest address is fixed because
> after
> > page table, code layout is fixed(4K for normal code, and another 4K only
> > contains reset vector code).
> > Today's implementation organizes the page table as following if 1G page
> > table is used:
> > 4G-16K: PML4 page (PML4[0] points to 4G-12K)
> > 4G-12K: PDP page
> > CR3 is set to 4G-16K
> > When 2M page table is used, the layout is as following:
> > 4G-32K: PML4 page (PML4[0] points to 4G-28K)
> > 4G-28K: PDP page (PDP entries point to PD pages)
> > 4G-24K: PD page mapping 0-1G
> > 4G-20K: PD page mapping 1-2G
> > 4G-16K: PD page mapping 2-3G
> > 4G-12K: PD page mapping 3-4G
> > CR3 is set to 4G-32K
> > CR3 doesn't point to a fixed location which is a bit hard to debug at runtime.
> >
> > The new page table layout will always put PML4 in highest address When
> 1G
> > page table is used, the layout is as following:
> > 4G-16K: PDP page
> > 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is
> used,
> > the layout is as following:
> > 4G-32K: PD page mapping 0-1G
> > 4G-28K: PD page mapping 1-2G
> > 4G-24K: PD page mapping 2-3G
> > 4G-20K: PD page mapping 3-4G
> > 4G-16K: PDP page (PDP entries point to PD pages)
> > 4G-12K: PML4 page (PML4[0] points to 4G-16K)
> > CR3 is always set to 4G-16K
>
> Zhiguang: This should be "CR3 is always set to 4G-12K"
>
> > So, this patch can improve debuggability by make sure the init
> > CR3 pointting to a fixed address(4G-12K).
> >
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Gerd Hoffmann <kraxel@redhat.com>
> > Cc: Debkumar De <debkumar.de@intel.com>
> > Cc: Catharine West <catharine.west@intel.com>
> > Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> > ---
> > .../ResetVector/Vtf0/Ia32/PageTables64.asm | 3 +-
> > UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 +
> > .../ResetVector/Vtf0/X64/PageTables1G.asm | 29 ++++++-------
> > .../ResetVector/Vtf0/X64/PageTables2M.asm | 43 +++++++++----------
> > 4 files changed, 37 insertions(+), 39 deletions(-)
> >
> > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> > b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> > index 87a4125d4b..717e380892 100644
> > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> > +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> > @@ -16,8 +16,9 @@ SetCr3ForPageTables64:
> >
> > ;
> > ; These pages are built into the ROM image in X64/PageTables.asm
> > + ; Highest level PageTable is at the highest address
> > ;
> > - mov eax, ADDR_OF(TopLevelPageDirectory)
> > + mov eax, ADDR_OF(PML4Table)
> > mov cr3, eax
> >
> > OneTimeCallRet SetCr3ForPageTables64 diff --git
> > a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> > b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> > index bdea1fb875..4b972a90a5 100644
> > --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> > +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
> > @@ -44,6 +44,7 @@
> > %include "X64/PageTables2M.asm"
> > %endif
> > %endif
> > +EndOfPageTables:
> >
> > %ifdef DEBUG_PORT80
> > %include "Port80Debug.asm"
> > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> > index 19bd3d5a92..a0f477b5b0 100644
> > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> > @@ -2,7 +2,7 @@
> > ; @file
> > ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000
> > (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> > +; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
> > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address
> Translation
> > to a 1-GByte Page ;
> > @@ -22,32 +22,29 @@ BITS 64
> > PAGE_PRESENT + \
> > PAGE_SIZE)
> >
> > -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define
> > PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
> > +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
> >
> > -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> > +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
> > PAGE_PDP_ATTR)
> >
> > %define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
> >
> > ALIGN 16
> > -
> > -TopLevelPageDirectory:
> > -
> > - ;
> > - ; Top level Page Directory Pointers (1 * 512GB entry)
> > - ;
> > - DQ PDP(0x1000)
> > -
> > - TIMES 0x1000-PGTBLS_OFFSET($) DB 0
> > +StartOfPageTables:
> > ;
> > - ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
> > + ; Page-directory pointer table Pointers (512 * 1GB entries => 512GB)
1. Page Directory Pointer Table (512 * 1GB entries => 512GB)
> > + ; Contains one page
> > ;
> > %assign i 0
> > %rep 512
> > DQ PDP_1G(i)
> > %assign i i+1
> > %endrep
> > - TIMES 0x2000-PGTBLS_OFFSET($) DB 0
> >
> > -EndOfPageTables:
> > +PML4Table:
2. "Pml4:"
> > + ;
> > + ; PML4 table Pointers (1 * 512GB entry)
> > + ;
> > + DQ PDP(0)
> > +
> > + TIMES 0x2000-PGTBLS_OFFSET($) DB 0
3: How about "TIMES 0x1000 - ($ - Pml4) DB 0"?
> > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> > index b97df384ac..0200825876 100644
> > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> > @@ -2,7 +2,7 @@
> > ; @file
> > ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000
> (4GB) ;
> > -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
> > +; Copyright (c) 2008 - 2023, Intel Corporation. All rights
> > +reserved.<BR>
> > ; SPDX-License-Identifier: BSD-2-Clause-Patent ;
> > ;------------------------------------------------------------------------------
> > @@ -21,40 +21,39 @@ BITS 64
> > PAGE_READ_WRITE + \
> > PAGE_PRESENT)
> >
> > -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define
> > PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
> > +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables)
> >
> > -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> > +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \
> > PAGE_PDP_ATTR)
> > %define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
> >
> > -TopLevelPageDirectory:
> > +ALIGN 16
> > +StartOfPageTables:
> >
> > ;
> > - ; Top level Page Directory Pointers (1 * 512GB entry)
> > + ; Page Table Entries (2048 * 2MB entries => 4GB)
4. "Page Directory (2048 * 2MB entries => 4GB)"
> > + ; Contains 4 pages
> > ;
> > - DQ PDP(0x1000)
> > -
> > +%assign i 0
> > +%rep 0x800
> > + DQ PTE_2MB(i)
> > + %assign i i+1
> > +%endrep
> >
> > ;
> > - ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
> > + ; Page-directory pointer table Pointers (4 * 1GB entries => 4GB)
> > + ; here is at offset 0x4000 from StartOfPageTables
> > ;
> > - TIMES 0x1000-PGTBLS_OFFSET($) DB 0
> > -
5. "Pdp:"
> > + DQ PDP(0)
> > + DQ PDP(0x1000)
> > DQ PDP(0x2000)
> > DQ PDP(0x3000)
> > - DQ PDP(0x4000)
> > - DQ PDP(0x5000)
> > + TIMES 0x5000-PGTBLS_OFFSET($) DB 0
6. How about "TIMES 0x1000 - ($ - Pdp) DB 0"?
> >
> > +PML4Table:
7. "Pml4:"
> > ;
> > - ; Page Table Entries (2048 * 2MB entries => 4GB)
> > + ; PML4 table Pointers (1 * 512GB entry)
> > ;
> > - TIMES 0x2000-PGTBLS_OFFSET($) DB 0
> > -
> > -%assign i 0
> > -%rep 0x800
> > - DQ PTE_2MB(i)
> > - %assign i i+1
> > -%endrep
> > + DQ PDP(0x4000)
> >
> > -EndOfPageTables:
> > + TIMES 0x6000-PGTBLS_OFFSET($) DB 0
8. How about "TIMES 0x1000 - ($ - Pml4) DB 0"?
> > --
> > 2.31.1.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table in ResetVector
2023-04-26 8:13 ` [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table " Zhiguang Liu
@ 2023-04-26 9:07 ` Ni, Ray
0 siblings, 0 replies; 5+ messages in thread
From: Ni, Ray @ 2023-04-26 9:07 UTC (permalink / raw)
To: Liu, Zhiguang, devel@edk2.groups.io
Cc: Dong, Eric, Kumar, Rahul R, Gerd Hoffmann, De, Debkumar,
West, Catharine
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: Wednesday, April 26, 2023 4:13 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; De,
> Debkumar <debkumar.de@intel.com>; West, Catharine
> <catharine.west@intel.com>
> Subject: [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table in
> ResetVector
>
> Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
> 5 level page table.
> If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
> at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
> 5level paging is supported, use PML5Table, otherwise, use PML4Table.
> If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
> paging is not created, and 4level paging is at (4G-12K) and be used.
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Debkumar De <debkumar.de@intel.com>
> Cc: Catharine West <catharine.west@intel.com>
> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> ---
> .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 24 ++++++++++++++++--
> .../ResetVector/Vtf0/Ia32/PageTables64.asm | 25 -------------------
> UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 ++-
> .../ResetVector/Vtf0/X64/PageTables5L.asm | 20 +++++++++++++++
> 4 files changed, 45 insertions(+), 28 deletions(-)
> delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
> create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables5L.asm
>
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
> b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
> index 6891397c2a..0b4a21061b 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm
> @@ -2,7 +2,7 @@
> ; @file
> ; Transition from 32 bit flat protected mode into 64 bit flat protected mode
> ;
> -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> ;
> ;------------------------------------------------------------------------------
> @@ -13,8 +13,28 @@ BITS 32
> ; Modified: EAX
> ;
> Transition32FlatTo64Flat:
> +%ifdef USE_5_LEVEL_PAGE_TABLE
> + mov eax, 0
> + cpuid
> + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07
> + jb NotSupport5LevelPaging ; 5level paging not support, downgrade
> to 4level paging
> + mov eax, 07h ; check cpuid leaf 7, subleaf 0
> + mov ecx, 0
> + cpuid
> + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1.
> + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade
> to 4level paging
> + mov eax, ADDR_OF(PML5Table)
1. Label can be "Pml5"
> + mov cr3, eax
> + mov eax, cr4
> + bts eax, 12 ; Set LA57=1.
> + mov cr4, eax
> + jmp CR3ProgramDone
> +NotSupport5LevelPaging:
> +%endif
>
> - OneTimeCall SetCr3ForPageTables64
> + mov eax, ADDR_OF(PML4Table)
> + mov cr3, eax
> +CR3ProgramDone:
2. Label can be "SetCr3Done"
> +
> +PML5Table:
3. "Pml5:"
> + ;
> + ; PML5 table Pointers
4. "PML5"
> + ; Assume page table is create from bottom to top, and only one PML4
> table there.
5. "Assume PML4 is in 4KB-lower address"
> + ;
> + DQ (ADDR_OF($) - 0x1000 + PAGE_PDP_ATTR)
> +
> + ;
> + ; Only first PML5 entry(first 8 bytes) pointting to a PML4 table. Others are
> zero
> + ;
> + TIMES (0x1000 - 0x8) DB 0
6. How about "TIMES 0x1000 - ($-Pml5) DB 0"?
> --
> 2.31.1.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-04-26 9:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2023-04-26 8:13 [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
2023-04-26 8:13 ` [PATCH v2 2/2] UefiCpuPkg: Support 5 level page table " Zhiguang Liu
2023-04-26 9:07 ` Ni, Ray
2023-04-26 8:25 ` [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table " Zhiguang Liu
2023-04-26 8:58 ` Ni, Ray
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