From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.13384.1682664196906836590 for ; Thu, 27 Apr 2023 23:43:17 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=anDFS2iy; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682664196; x=1714200196; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=/YHWU0+ROqD5EZ1OSLEh9jWJaHnrVjBC7LYNNbNQiEY=; b=anDFS2iyk3D7NIzk8GKAN7juXKIHUPdOaycdGI7nz+EL+MjH1HleH5c4 WHL0IfXbSV7nkj2BhrUoo77KrcNkJCTlSXEl5jgw6yLnAtYs0vSAfL3k6 MdphdqdvFq64jxurn/280UJTypJKv1AtjYU17h9d6hupMLhx4jx9vosbN nogezGf8Xjtx3Dgf1UJNTtJY0+LgvgebBiQrqvR1f1MWiVbrNWZaYp4I4 uXAJ1qG5RCc0rrxcY/BsjHx4Kth1GakspMMWArjBg420rGr0PvrHbzIje wvA5unRBKaU83CCtI2FLh6Pmz0oWQVwoMRFmcRCqOOxVLCdZzS61kawIG A==; X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="433956808" X-IronPort-AV: E=Sophos;i="5.99,233,1677571200"; d="scan'208";a="433956808" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2023 23:43:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="806262923" X-IronPort-AV: E=Sophos;i="5.99,233,1677571200"; d="scan'208";a="806262923" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2023 23:43:02 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [PATCH v3 1/5] UefiCpuPkg/ResetVector: Rename macros about page table. Date: Fri, 28 Apr 2023 14:42:19 +0800 Message-Id: <20230428064223.2048-1-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PG_NLE (no leaf entry) is better. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/X64/PageTables1G.asm | 24 ++++++++++---- .../ResetVector/Vtf0/X64/PageTables2M.asm | 33 +++++++++++-------- 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm index 19bd3d5a92..97e90777c8 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation to a 1-GByte Page ; @@ -12,11 +12,18 @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ +; +; Page table no-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ +; +; Page table big leaf page attribute +; Big leaf page contains PDPTE 1GB page and PDE 2MB page +; +%define PAGE_BLP_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_DIRTY + \ PAGE_PRESENT + \ @@ -25,10 +32,13 @@ BITS 64 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) +; +; Page table no-leaf entry +; +%define PG_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) +%define PDP_1G(x) ((x << 30) + PAGE_BLP_ATTR) ALIGN 16 @@ -37,7 +47,7 @@ TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PG_NLE(0x1000) TIMES 0x1000-PGTBLS_OFFSET($) DB 0 ; diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm index b97df384ac..e46694c799 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ; -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -11,29 +11,36 @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \ +; +; Page table big leaf page attribute +; Big leaf page contains PDPTE 1GB page and PDE 2MB page +; +%define PAGE_BLP_ATTR (PAGE_SIZE + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) +; +; Page table no-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) +%define PG_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) +%define PTE_2MB(x) ((x << 21) + PAGE_BLP_ATTR) TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PG_NLE(0x1000) ; @@ -41,10 +48,10 @@ TopLevelPageDirectory: ; TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - DQ PDP(0x2000) - DQ PDP(0x3000) - DQ PDP(0x4000) - DQ PDP(0x5000) + DQ PG_NLE(0x2000) + DQ PG_NLE(0x3000) + DQ PG_NLE(0x4000) + DQ PG_NLE(0x5000) ; ; Page Table Entries (2048 * 2MB entries => 4GB) -- 2.31.1.windows.1